[Mesa-dev] [PATCH] i965/hsw: compute DDX in a subspan based only on top row

[Mark Mueller]

Wow, it's not often we as developers get to attribute an unexplained
performance improvement to silicon. I'm happy to say I guessed wrong here.

Did this start specifically with Haswell and is it likely this will persist
in future gen hardware - more specifically, what's the proper test by the
driver for availability of this feature in hardware?

Finally, were any other silicon improvements revealed besides what Chai-I
was able to expose?

Mark


On Fri, Sep 20, 2013 at 12:51 PM, Kenneth Graunke <kenneth at whitecape.org>wrote:

> On 09/20/2013 08:30 AM, Ian Romanick wrote:
> > On 09/20/2013 09:50 AM, Paul Berry wrote:
> [snip]
> >> Since the SAMPLER_MODE setting allows us to trade off quality vs
> >> performance, we're also interested to know whether a value less than
> >> 0x1f is sufficient to produce the performance improvement in Xonotic--it
> >> would be nice if we could find a "sweet spot" for this setting that
> >> produces the performance improvement we need without sacrificing too
> >> much quality.
> >
> > How about if we just give a driconf option to adjust it.  Then gamers
> > can make their own choice.  For applications where it know it makes a
> > big difference, we can provide a default non-0 value in the system
> driconf.
>
> Because you can't (yet) program registers from userspace unless you're
> root.
>
> I would like to use the same default value as Windows.  I'm fine with
> making it tunable beyond that.
>
> --Ken
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.freedesktop.org/archives/mesa-dev/attachments/20130920/09ddb11f/attachment.html>