[Mesa-dev] [PATCH 07/29] i965: Add the family name to the PCI ID table.
Kenneth Graunke
kenneth at whitecape.org
Fri Sep 27 16:45:46 PDT 2013
I removed this a while ago, since we never used it, but I'm finally
resurrecting the idea in the next commits.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
include/pci_ids/i965_pci_ids.h | 186 +++++++++++++++---------------
include/pci_ids/pci_id_driver_map.h | 2 +-
src/mesa/drivers/dri/i965/intel_context.c | 2 +-
3 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 00d2737..9d38a4a 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -1,93 +1,93 @@
-CHIPSET(0x29A2, "Intel(R) 965G")
-CHIPSET(0x2992, "Intel(R) 965Q")
-CHIPSET(0x2982, "Intel(R) 965G")
-CHIPSET(0x2972, "Intel(R) 946GZ")
-CHIPSET(0x2A02, "Intel(R) 965GM")
-CHIPSET(0x2A12, "Intel(R) 965GME/GLE")
-CHIPSET(0x2A42, "Mobile Intel® GM45 Express Chipset")
-CHIPSET(0x2E02, "Intel(R) Integrated Graphics Device")
-CHIPSET(0x2E12, "Intel(R) Q45/Q43")
-CHIPSET(0x2E22, "Intel(R) G45/G43")
-CHIPSET(0x2E32, "Intel(R) G41")
-CHIPSET(0x2E42, "Intel(R) B43")
-CHIPSET(0x2E92, "Intel(R) B43")
-CHIPSET(0x0042, "Intel(R) Ironlake Desktop")
-CHIPSET(0x0046, "Intel(R) Ironlake Mobile")
-CHIPSET(0x0102, "Intel(R) Sandybridge Desktop")
-CHIPSET(0x0112, "Intel(R) Sandybridge Desktop")
-CHIPSET(0x0122, "Intel(R) Sandybridge Desktop")
-CHIPSET(0x0106, "Intel(R) Sandybridge Mobile")
-CHIPSET(0x0116, "Intel(R) Sandybridge Mobile")
-CHIPSET(0x0126, "Intel(R) Sandybridge Mobile")
-CHIPSET(0x010A, "Intel(R) Sandybridge Server")
-CHIPSET(0x0152, "Intel(R) Ivybridge Desktop")
-CHIPSET(0x0162, "Intel(R) Ivybridge Desktop")
-CHIPSET(0x0156, "Intel(R) Ivybridge Mobile")
-CHIPSET(0x0166, "Intel(R) Ivybridge Mobile")
-CHIPSET(0x015a, "Intel(R) Ivybridge Server")
-CHIPSET(0x016a, "Intel(R) Ivybridge Server")
-CHIPSET(0x0402, "Intel(R) Haswell Desktop")
-CHIPSET(0x0412, "Intel(R) Haswell Desktop")
-CHIPSET(0x0422, "Intel(R) Haswell Desktop")
-CHIPSET(0x0406, "Intel(R) Haswell Mobile")
-CHIPSET(0x0416, "Intel(R) Haswell Mobile")
-CHIPSET(0x0426, "Intel(R) Haswell Mobile")
-CHIPSET(0x040A, "Intel(R) Haswell Server")
-CHIPSET(0x041A, "Intel(R) Haswell Server")
-CHIPSET(0x042A, "Intel(R) Haswell Server")
-CHIPSET(0x040B, "Intel(R) Haswell")
-CHIPSET(0x041B, "Intel(R) Haswell")
-CHIPSET(0x042B, "Intel(R) Haswell")
-CHIPSET(0x040E, "Intel(R) Haswell")
-CHIPSET(0x041E, "Intel(R) Haswell")
-CHIPSET(0x042E, "Intel(R) Haswell")
-CHIPSET(0x0C02, "Intel(R) Haswell Desktop")
-CHIPSET(0x0C12, "Intel(R) Haswell Desktop")
-CHIPSET(0x0C22, "Intel(R) Haswell Desktop")
-CHIPSET(0x0C06, "Intel(R) Haswell Mobile")
-CHIPSET(0x0C16, "Intel(R) Haswell Mobile")
-CHIPSET(0x0C26, "Intel(R) Haswell Mobile")
-CHIPSET(0x0C0A, "Intel(R) Haswell Server")
-CHIPSET(0x0C1A, "Intel(R) Haswell Server")
-CHIPSET(0x0C2A, "Intel(R) Haswell Server")
-CHIPSET(0x0C0B, "Intel(R) Haswell")
-CHIPSET(0x0C1B, "Intel(R) Haswell")
-CHIPSET(0x0C2B, "Intel(R) Haswell")
-CHIPSET(0x0C0E, "Intel(R) Haswell")
-CHIPSET(0x0C1E, "Intel(R) Haswell")
-CHIPSET(0x0C2E, "Intel(R) Haswell")
-CHIPSET(0x0A02, "Intel(R) Haswell Desktop")
-CHIPSET(0x0A12, "Intel(R) Haswell Desktop")
-CHIPSET(0x0A22, "Intel(R) Haswell Desktop")
-CHIPSET(0x0A06, "Intel(R) Haswell Mobile")
-CHIPSET(0x0A16, "Intel(R) Haswell Mobile")
-CHIPSET(0x0A26, "Intel(R) Haswell Mobile")
-CHIPSET(0x0A0A, "Intel(R) Haswell Server")
-CHIPSET(0x0A1A, "Intel(R) Haswell Server")
-CHIPSET(0x0A2A, "Intel(R) Haswell Server")
-CHIPSET(0x0A0B, "Intel(R) Haswell")
-CHIPSET(0x0A1B, "Intel(R) Haswell")
-CHIPSET(0x0A2B, "Intel(R) Haswell")
-CHIPSET(0x0A0E, "Intel(R) Haswell")
-CHIPSET(0x0A1E, "Intel(R) Haswell")
-CHIPSET(0x0A2E, "Intel(R) Haswell")
-CHIPSET(0x0D02, "Intel(R) Haswell Desktop")
-CHIPSET(0x0D12, "Intel(R) Haswell Desktop")
-CHIPSET(0x0D22, "Intel(R) Haswell Desktop")
-CHIPSET(0x0D06, "Intel(R) Haswell Mobile")
-CHIPSET(0x0D16, "Intel(R) Haswell Mobile")
-CHIPSET(0x0D26, "Intel(R) Haswell Mobile")
-CHIPSET(0x0D0A, "Intel(R) Haswell Server")
-CHIPSET(0x0D1A, "Intel(R) Haswell Server")
-CHIPSET(0x0D2A, "Intel(R) Haswell")
-CHIPSET(0x0D0B, "Intel(R) Haswell")
-CHIPSET(0x0D1B, "Intel(R) Haswell")
-CHIPSET(0x0D2B, "Intel(R) Haswell")
-CHIPSET(0x0D0E, "Intel(R) Haswell")
-CHIPSET(0x0D1E, "Intel(R) Haswell")
-CHIPSET(0x0D2E, "Intel(R) Haswell")
-CHIPSET(0x0F31, "Intel(R) Bay Trail")
-CHIPSET(0x0F32, "Intel(R) Bay Trail")
-CHIPSET(0x0F33, "Intel(R) Bay Trail")
-CHIPSET(0x0157, "Intel(R) Bay Trail")
-CHIPSET(0x0155, "Intel(R) Bay Trail")
+CHIPSET(0x29A2, i965, "Intel(R) 965G")
+CHIPSET(0x2992, i965, "Intel(R) 965Q")
+CHIPSET(0x2982, i965, "Intel(R) 965G")
+CHIPSET(0x2972, i965, "Intel(R) 946GZ")
+CHIPSET(0x2A02, i965, "Intel(R) 965GM")
+CHIPSET(0x2A12, i965, "Intel(R) 965GME/GLE")
+CHIPSET(0x2A42, g4x, "Mobile Intel® GM45 Express Chipset")
+CHIPSET(0x2E02, g4x, "Intel(R) Integrated Graphics Device")
+CHIPSET(0x2E12, g4x, "Intel(R) Q45/Q43")
+CHIPSET(0x2E22, g4x, "Intel(R) G45/G43")
+CHIPSET(0x2E32, g4x, "Intel(R) G41")
+CHIPSET(0x2E42, g4x, "Intel(R) B43")
+CHIPSET(0x2E92, g4x, "Intel(R) B43")
+CHIPSET(0x0042, ilk, "Intel(R) Ironlake Desktop")
+CHIPSET(0x0046, ilk, "Intel(R) Ironlake Mobile")
+CHIPSET(0x0102, snb_gt1, "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0112, snb_gt2, "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0122, snb_gt2, "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0106, snb_gt1, "Intel(R) Sandybridge Mobile")
+CHIPSET(0x0116, snb_gt2, "Intel(R) Sandybridge Mobile")
+CHIPSET(0x0126, snb_gt2, "Intel(R) Sandybridge Mobile")
+CHIPSET(0x010A, snb_gt1, "Intel(R) Sandybridge Server")
+CHIPSET(0x0152, ivb_gt1, "Intel(R) Ivybridge Desktop")
+CHIPSET(0x0162, ivb_gt2, "Intel(R) Ivybridge Desktop")
+CHIPSET(0x0156, ivb_gt1, "Intel(R) Ivybridge Mobile")
+CHIPSET(0x0166, ivb_gt2, "Intel(R) Ivybridge Mobile")
+CHIPSET(0x015a, ivb_gt1, "Intel(R) Ivybridge Server")
+CHIPSET(0x016a, ivb_gt2, "Intel(R) Ivybridge Server")
+CHIPSET(0x0402, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0412, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0422, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0406, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0416, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0426, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x040A, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x041A, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x042A, hsw_gt3, "Intel(R) Haswell Server")
+CHIPSET(0x040B, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x041B, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x042B, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x040E, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x041E, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x042E, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0C02, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0C12, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0C22, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0C06, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0C16, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0C26, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x0C0A, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x0C1A, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x0C2A, hsw_gt3, "Intel(R) Haswell Server")
+CHIPSET(0x0C0B, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0C1B, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0C2B, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0C0E, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0C1E, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0C2E, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0A02, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0A12, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0A22, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0A06, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0A16, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0A26, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x0A0A, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x0A1A, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x0A2A, hsw_gt3, "Intel(R) Haswell Server")
+CHIPSET(0x0A0B, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0A1B, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0A2B, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0A0E, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0A1E, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0A2E, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0D02, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0D12, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0D22, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0D06, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0D16, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0D26, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x0D0A, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x0D1A, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x0D2A, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0D0B, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0D1B, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0D2B, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0D0E, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0D1E, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0D2E, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0F31, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0F32, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0F33, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0157, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0155, byt, "Intel(R) Bay Trail")
diff --git a/include/pci_ids/pci_id_driver_map.h b/include/pci_ids/pci_id_driver_map.h
index e494a6d..8a97c6f 100644
--- a/include/pci_ids/pci_id_driver_map.h
+++ b/include/pci_ids/pci_id_driver_map.h
@@ -14,7 +14,7 @@ static const int i915_chip_ids[] = {
};
static const int i965_chip_ids[] = {
-#define CHIPSET(chip, name) chip,
+#define CHIPSET(chip, family, name) chip,
#include "pci_ids/i965_pci_ids.h"
#undef CHIPSET
};
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index fa8e705..154b052 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -70,7 +70,7 @@ intelGetString(struct gl_context * ctx, GLenum name)
case GL_RENDERER:
switch (brw->intelScreen->deviceID) {
#undef CHIPSET
-#define CHIPSET(id, str) case id: chipset = str; break;
+#define CHIPSET(id, family, str) case id: chipset = str; break;
#include "pci_ids/i965_pci_ids.h"
default:
chipset = "Unknown Intel Chipset";
--
1.8.3.4
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