[Mesa-dev] [PATCH 06/20] i965: Merge max_grf between stage compilers
Topi Pohjolainen
topi.pohjolainen at intel.com
Fri Apr 11 00:28:46 PDT 2014
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 --
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 1 -
src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_shader.h | 3 +++
src/mesa/drivers/dri/i965/brw_vec4.h | 1 -
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 --
7 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 95a7ff4..4f3a61d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -531,8 +531,6 @@ public:
fs_reg dual_src_output;
bool do_dual_src;
int first_non_payload_grf;
- /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
- int max_grf;
fs_reg *fp_temp_regs;
fs_reg *fp_input_regs;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index f2f158e..d944f16 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -63,7 +63,7 @@ fs_visitor::assign_regs_trivial()
assign_reg(hw_reg_mapping, &inst->src[2], reg_width);
}
- if (this->grf_used >= max_grf) {
+ if ((unsigned)this->grf_used >= max_grf) {
fail("Ran out of regs on trivial allocator (%d/%d)\n",
this->grf_used, max_grf);
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 790d799..c044f91 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2968,7 +2968,6 @@ fs_visitor::fs_visitor(struct brw_context *brw,
memset(this->outputs, 0, sizeof(this->outputs));
memset(this->output_components, 0, sizeof(this->output_components));
this->first_non_payload_grf = 0;
- this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->current_annotation = NULL;
this->base_ir = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index bac76a6..26e939f 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -551,7 +551,8 @@ backend_visitor::backend_visitor(struct gl_shader_program *shader_prog,
backend_emitter::backend_emitter(struct brw_context *brw)
: brw(brw),
ctx(&brw->ctx),
- mem_ctx(ralloc_context(NULL))
+ mem_ctx(ralloc_context(NULL)),
+ max_grf(brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF)
{
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 20b621d..3d6e679 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -106,6 +106,9 @@ public:
*/
exec_list instructions;
+ /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
+ const unsigned max_grf;
+
virtual void dump_instruction(backend_instruction *inst) = 0;
virtual void dump_instructions();
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 0c47618..75965ef 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -337,7 +337,6 @@ public:
int virtual_grf_count;
int virtual_grf_array_size;
int first_non_payload_grf;
- unsigned int max_grf;
int *virtual_grf_start;
int *virtual_grf_end;
dst_reg userplane[MAX_CLIP_PLANES];
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c63a90b..bd00ce3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3385,8 +3385,6 @@ vec4_visitor::vec4_visitor(struct brw_context *brw,
this->virtual_grf_array_size = 0;
this->live_intervals_valid = false;
- this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
-
this->uniforms = 0;
/* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
--
1.8.3.1
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