[Mesa-dev] [PATCH 14/20] i965/fs: Add support for W-tiled coordinate swizzling
Topi Pohjolainen
topi.pohjolainen at intel.com
Fri Apr 11 00:28:54 PDT 2014
---
src/mesa/drivers/dri/i965/brw_fs.h | 4 ++++
src/mesa/drivers/dri/i965/brw_fs_emitter.cpp | 23 +++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 26e5545..a30351d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -291,6 +291,10 @@ protected:
fs_inst *emit(fs_inst *inst);
void emit(exec_list list);
+ void emit_coord_swizzling(const fs_reg& t1,
+ const fs_reg& x,
+ const fs_reg& y);
+
void push_force_uncompressed();
void pop_force_uncompressed();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp b/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp
index 74500fb..22fa33d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emitter.cpp
@@ -185,6 +185,29 @@ fs_emitter::pop_force_uncompressed()
assert(force_uncompressed_stack >= 0);
}
+void
+fs_emitter::emit_coord_swizzling(const fs_reg& t1,
+ const fs_reg& x,
+ const fs_reg& y)
+{
+ fs_inst* inst;
+
+ /* If 4th bit is set in x-coord, the 4th bit in y-coord gets flipped */
+ emit(AND(t1, x, brw_imm_uw(0x8))); /* x & 0x8 */
+ inst = emit(BRW_OPCODE_CMP, reg_null_f, t1, brw_imm_uw(0));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ emit(BRW_OPCODE_IF);
+ emit(AND(t1, y, brw_imm_uw(0x8))); /* y & 0x8 */
+ inst = emit(BRW_OPCODE_CMP, reg_null_f, t1, brw_imm_uw(0));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ emit(BRW_OPCODE_IF);
+ inst = emit(AND(y, y, brw_imm_uw(0xfff7)));
+ emit(BRW_OPCODE_ELSE);
+ inst = emit(OR(y, y, brw_imm_uw(0x8)));
+ emit(BRW_OPCODE_ENDIF);
+ emit(BRW_OPCODE_ENDIF);
+}
+
fs_emitter::fs_emitter(struct brw_context *brw,
struct brw_wm_compile *c,
unsigned dispatch_width)
--
1.8.3.1
More information about the mesa-dev
mailing list