[Mesa-dev] [PATCH v2 0/6] gallium: add new opcodes needed for ARB_gs5

[Roland Scheidegger]

For 1-4:
Reviewed-by: Roland Scheidegger <sroland at vmware.com>

Am 26.04.2014 18:16, schrieb Ilia Mirkin:
> v1 -> v2:
>  - improved docs and comments
>  - nvc0 support for new opcodes
>  - split out math helpers into separate commit
> 
> I'm pretty sure I addressed all the feedback in the earlier series. Let me
> know if I missed anything.
> 
> Ilia Mirkin (6):
>   gallium: add new opcodes for ARB_gs5 bit manipulation support
>   mesa/st: implement new bit manipulation opcodes
>   gallium/util: add helpers for bitfield manipulation
>   tgsi: add tgsi_exec support for new bit manipulation opcodes
>   nvc0/ir: add support for new bitfield manipulation opcodes
>   nvc0/ir: add support for MUL_HI tgsi opcodes
> 
>  src/gallium/auxiliary/tgsi/tgsi_exec.c             | 172 +++++++++++++++++++++
>  src/gallium/auxiliary/tgsi/tgsi_info.c             |   8 +
>  src/gallium/auxiliary/util/u_math.h                |  31 ++++
>  src/gallium/docs/source/tgsi.rst                   |  75 +++++++++
>  src/gallium/drivers/nouveau/codegen/nv50_ir.h      |   2 +
>  .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp |  35 +++++
>  .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  |  17 ++
>  .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  77 ++++++++-
>  .../drivers/nouveau/codegen/nv50_ir_print.cpp      |   1 +
>  .../drivers/nouveau/codegen/nv50_ir_target.cpp     |   5 +-
>  .../nouveau/codegen/nv50_ir_target_nvc0.cpp        |   7 +-
>  src/gallium/include/pipe/p_shader_tokens.h         |  11 +-
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp         |  73 +++++++--
>  13 files changed, 491 insertions(+), 23 deletions(-)
>