[Mesa-dev] [PATCH 0/4] gallium: add new opcodes needed for ARB_gs5

[Matt Turner]

On Fri, Apr 25, 2014 at 12:52 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
> And then you have a peephole pass that looks for this and converts it
> into a single instruction. Additionally this has the advantage of
> working on code where people manually implemented uaddCarry (although
> there are other ways to implement it, and this would only detect one
> of them).

CMP on i965 returns 0 or 0xFFFFFFFF rather than 0 or 1. It also
unconditionally writes the flag register, which won't be used, and
will only cause scheduling conflicts.

I think I'd prefer you do a carry -> SLT lowering pass until I have a
peephole pass in place. But I'm also not really concerned about
performance from this at the moment either...