[Mesa-dev] [PATCH v3 06/19] i965/gen6_depth_state.c: Remove (gen < 6) code paths

[Jordan Justen]

Since this code was branched from brw_misc_state.c, it had support for
gen < 6. We can now remove this.

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/gen6_depth_state.c | 40 +++++++++-------------------
 1 file changed, 13 insertions(+), 27 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index d37aae8..2cb60b3 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -63,16 +63,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
       intel_emit_depth_stall_flushes(brw);
    }
 
-   unsigned int len;
-   if (brw->gen >= 6)
-      len = 7;
-   else if (brw->is_g4x || brw->gen == 5)
-      len = 6;
-   else
-      len = 5;
-
-   BEGIN_BATCH(len);
-   OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
+   BEGIN_BATCH(7);
+   OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
    OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
              (depthbuffer_format << 18) |
              ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
@@ -94,13 +86,9 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
              ((height + tile_y - 1) << 19));
    OUT_BATCH(0);
 
-   if (brw->is_g4x || brw->gen >= 5)
-      OUT_BATCH(tile_x | (tile_y << 16));
-   else
-      assert(tile_x == 0 && tile_y == 0);
+   OUT_BATCH(tile_x | (tile_y << 16));
 
-   if (brw->gen >= 6)
-      OUT_BATCH(0);
+   OUT_BATCH(0);
 
    ADVANCE_BATCH();
 
@@ -162,15 +150,13 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
     */
-   if (brw->gen >= 6 || hiz) {
-      if (brw->gen == 6)
-	 intel_emit_post_sync_nonzero_flush(brw);
-
-      BEGIN_BATCH(2);
-      OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
-		GEN5_DEPTH_CLEAR_VALID |
-		(2 - 2));
-      OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
-      ADVANCE_BATCH();
-   }
+   if (brw->gen == 6)
+      intel_emit_post_sync_nonzero_flush(brw);
+
+   BEGIN_BATCH(2);
+   OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
+             GEN5_DEPTH_CLEAR_VALID |
+             (2 - 2));
+   OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
+   ADVANCE_BATCH();
 }
-- 
2.0.1