[Mesa-dev] [PATCH v3 11/19] i965/gen6 blorp depth: calculate base surface width/height

[Pohjolainen, Topi]

On Fri, Aug 01, 2014 at 12:53:41AM -0700, Jordan Justen wrote:
> (e3a49e1 for gen6)
> 
> This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
> 
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>

Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

> ---
>  src/mesa/drivers/dri/i965/gen6_blorp.cpp | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> index ff1732d..dca6bfc 100644
> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> @@ -791,6 +791,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
>     uint32_t draw_x = params->depth.x_offset;
>     uint32_t draw_y = params->depth.y_offset;
>     uint32_t tile_mask_x, tile_mask_y;
> +   uint32_t surfwidth, surfheight;
>     uint32_t surftype;
>     unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
>     unsigned int min_array_element;
> @@ -823,6 +824,18 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
>  
>     lod = params->depth.level - params->depth.mt->first_level;
>  
> +   if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
> +      /* HIZ ops for lod 0 may set the width & height a little
> +       * larger to allow the fast depth clear to fit the hardware
> +       * alignment requirements. (8x4)
> +       */
> +      surfwidth = params->depth.width;
> +      surfheight = params->depth.height;
> +   } else {
> +      surfwidth = params->depth.mt->logical_width0;
> +      surfheight = params->depth.mt->logical_height0;
> +   }
> +
>     /* 3DSTATE_DEPTH_BUFFER */
>     {
>        uint32_t tile_x = draw_x & tile_mask_x;
> -- 
> 2.0.1
> 
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev