[Mesa-dev] [PATCH 07/12] i965: Provide a context flag to let us enable fast clear
Kristian Høgsberg
krh at bitplanet.net
Mon Aug 11 17:29:37 PDT 2014
GEN7+ has the fast clear functionality, which lets us clear the color
buffers using the MCS and a scaled down rectangle. To enable this
we have to set the appropriate bits in the 3DSTATE_PS package.
Signed-off-by: Kristian Høgsberg <krh at bitplanet.net>
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 ++
src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 ++
3 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 6ab7713..c4bb4dc 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1252,6 +1252,7 @@ struct brw_context
* Gen6. See brw_update_null_renderbuffer_surface().
*/
drm_intel_bo *multisampled_null_render_target_bo;
+ uint32_t fast_clear_op;
} wm;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index c3e9316..278cf17 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -246,6 +246,8 @@ upload_ps_state(struct brw_context *brw)
ksp0 = brw->wm.base.prog_offset;
}
+ dw4 |= brw->wm.fast_clear_op;
+
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
OUT_BATCH(ksp0);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 49d4fe0..5e313bf 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -185,6 +185,8 @@ upload_ps_state(struct brw_context *brw)
else
dw6 |= GEN7_PS_POSOFFSET_NONE;
+ dw6 |= brw->wm.fast_clear_op;
+
/* _NEW_MULTISAMPLE
* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
* should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
--
2.0.0
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