[Mesa-dev] [PATCH 1/2] radeonsi: turn off PARTIAL_VS_WAVE and bump PRIMGROUP_SIZE, do the same for SI

[Alex Deucher]

On Mon, Aug 11, 2014 at 4:39 PM, Marek Olšák <maraeo at gmail.com> wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> These are recommended values. Some additional tweeks will be needed
> for tessellation.

For the series:

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  src/gallium/drivers/radeonsi/si_state.c      |  6 -----
>  src/gallium/drivers/radeonsi/si_state_draw.c | 33 ++++++++++++++++------------
>  2 files changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 6e9a60a..e85f601 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3013,12 +3013,6 @@ void si_init_config(struct si_context *sctx)
>         si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
>
>         si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
> -       if (sctx->b.chip_class == SI) {
> -               si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
> -                              S_028AA8_SWITCH_ON_EOP(1) |
> -                              S_028AA8_PARTIAL_VS_WAVE_ON(1) |
> -                              S_028AA8_PRIMGROUP_SIZE(63));
> -       }
>         si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
>         si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
>         if (sctx->b.chip_class < CIK)
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 411ea04..15e6bac 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -384,12 +384,17 @@ static bool si_update_draw_info_state(struct si_context *sctx,
>  {
>         struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
>         struct si_shader *vs = si_get_vs_state(sctx);
> +       struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
>         unsigned prim = si_conv_pipe_prim(info->mode);
>         unsigned gs_out_prim =
>                 si_conv_prim_to_gs_out(sctx->gs_shader ?
>                                        sctx->gs_shader->current->shader.gs_output_prim :
>                                        info->mode);
>         unsigned ls_mask = 0;
> +       unsigned primgroup_size = 256;
> +       /* SWITCH_ON_EOP(0) is always preferable. */
> +       bool wd_switch_on_eop = false;
> +       bool ia_switch_on_eop = false;
>
>         if (pm4 == NULL)
>                 return false;
> @@ -399,14 +404,17 @@ static bool si_update_draw_info_state(struct si_context *sctx,
>                 return false;
>         }
>
> -       if (sctx->b.chip_class >= CIK) {
> -               struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
> -               unsigned primgroup_size = 64;
> +       if (prim == V_008958_DI_PT_TRISTRIP_ADJ)
> +               primgroup_size = 128;
>
> -               /* SWITCH_ON_EOP(0) is always preferable. */
> -               bool wd_switch_on_eop = false;
> -               bool ia_switch_on_eop = false;
> +       /* This is a hardware requirement. */
> +       if ((rs && rs->line_stipple_enable) ||
> +           (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
> +               ia_switch_on_eop = true;
> +               wd_switch_on_eop = true;
> +       }
>
> +       if (sctx->b.chip_class >= CIK) {
>                 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
>                  * 4 shader engines. Set 1 to pass the assertion below.
>                  * The other cases are hardware requirements. */
> @@ -425,13 +433,6 @@ static bool si_update_draw_info_state(struct si_context *sctx,
>                     (info->indirect || info->instance_count > 1))
>                         wd_switch_on_eop = true;
>
> -               /* This is a hardware requirement. */
> -               if ((rs && rs->line_stipple_enable) ||
> -                   (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
> -                       ia_switch_on_eop = true;
> -                       wd_switch_on_eop = true;
> -               }
> -
>                 /* If the WD switch is false, the IA switch must be false too. */
>                 assert(wd_switch_on_eop || !ia_switch_on_eop);
>
> @@ -442,13 +443,17 @@ static bool si_update_draw_info_state(struct si_context *sctx,
>                 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
>                 si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
>                                S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
> -                              S_028AA8_PARTIAL_VS_WAVE_ON(1) |
> +                              S_028AA8_PARTIAL_VS_WAVE_ON(0) |
>                                S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
>                                S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
>                 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
>                 si_pm4_cmd_end(pm4, false);
>         } else {
>                 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
> +               si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
> +                              S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
> +                              S_028AA8_PARTIAL_VS_WAVE_ON(0) |
> +                              S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
>         }
>
>         si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
> --
> 1.9.1
>
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