[Mesa-dev] [PATCH 25/37] i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcode

[Iago Toral Quiroga]

From: Samuel Iglesias Gonsalvez <siglesias at igalia.com>

This opcode generates code to copy the specified destination index
into subregister 5 of the MRF message header.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h          |  9 +++++++++
 src/mesa/drivers/dri/i965/brw_shader.cpp         |  2 ++
 src/mesa/drivers/dri/i965/brw_vec4.h             |  4 ++++
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 20 ++++++++++++++++++++
 4 files changed, 35 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 83011d6..7095c39 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1052,6 +1052,15 @@ enum opcode {
     * - src1 is the destination register when write commit occurs.
     */
    GS_OPCODE_SVB_WRITE,
+
+   /**
+    * Set destination index in the SVB write message payload (M0.5). Used
+    * in gen6 for transform feedback.
+    *
+    * - dst is the header to save the destination indices for SVB WRITE.
+    * - src is the register that holds the destination indices value.
+    */
+   GS_OPCODE_SVB_SET_DST_INDEX,
 };
 
 enum brw_urb_write_flags {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 8698b75..bf625a5 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -538,6 +538,8 @@ brw_instruction_name(enum opcode op)
       return "set_primitive_id";
    case GS_OPCODE_SVB_WRITE:
       return "gs_svb_write";
+   case GS_OPCODE_SVB_SET_DST_INDEX:
+      return "gs_svb_set_dst_index";
 
    default:
       /* Yes, this leaks.  It's in debug code, it should never occur, and if
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index e8456ce..ea3967d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -222,6 +222,7 @@ public:
 
    unsigned sol_binding; /**< gen6: SOL binding table index */
    bool sol_final_write; /**< gen6: send commit message */
+   unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 
    bool is_send_from_grf();
    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
@@ -664,6 +665,9 @@ private:
                               struct brw_reg dst,
                               struct brw_reg src0,
                               struct brw_reg src1);
+   void generate_gs_svb_set_destination_index(vec4_instruction *inst,
+                                              struct brw_reg dst,
+                                              struct brw_reg src);
    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
    void generate_gs_prepare_channel_masks(struct brw_reg dst);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 1728790..d914a52 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -574,6 +574,22 @@ vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
 }
 
 void
+vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
+                                                      struct brw_reg dst,
+                                                      struct brw_reg src)
+{
+
+   int vertex = inst->sol_vertex;
+   brw_push_insn_state(p);
+   brw_set_default_access_mode(p, BRW_ALIGN_1);
+   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+   brw_MOV(p, get_element_ud(dst, 5),
+           get_element_ud(src, vertex));
+   brw_set_default_access_mode(p, BRW_ALIGN_16);
+   brw_pop_insn_state(p);
+}
+
+void
 vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
                                               struct brw_reg src)
 {
@@ -1313,6 +1329,10 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
    case GS_OPCODE_SVB_WRITE:
       generate_gs_svb_write(inst, dst, src[0], src[1]);
 
+   case GS_OPCODE_SVB_SET_DST_INDEX:
+      generate_gs_svb_set_destination_index(inst, dst, src[0]);
+      break;
+
    case GS_OPCODE_SET_DWORD_2_IMMED:
       generate_gs_set_dword_2_immed(dst, src[0]);
       break;
-- 
1.9.1