[Mesa-dev] [PATCH] r600g: Implement ARB_derivative_control

[Ilia Mirkin]

On Thu, Aug 14, 2014 at 12:57 PM, Glenn Kennard <glenn.kennard at gmail.com> wrote:
> Requires Evergreen/Cayman
>
> Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
> ---
> Passes ARB_derivative_control piglit tests, no regressions.
> Depends on Ilia's derivative control gallium infrastructure
> patches.

FYI, I pushed these out. However note that I changed the opcodes to
instead fill some gaps as per Marek's suggestions, so your patch will
require some trivial updates.

>
>  docs/GL3.txt                           |  2 +-
>  src/gallium/drivers/r600/r600_pipe.c   |  2 +-
>  src/gallium/drivers/r600/r600_shader.c | 20 ++++++++++++++++++++
>  3 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/docs/GL3.txt b/docs/GL3.txt
> index 9eba525..202dbed 100644
> --- a/docs/GL3.txt
> +++ b/docs/GL3.txt
> @@ -188,7 +188,7 @@ GL 4.5, GLSL 4.50:
>    GL_ARB_clip_control                                  not started
>    GL_ARB_conditional_render_inverted                   not started
>    GL_ARB_cull_distance                                 not started
> -  GL_ARB_derivative_control                            not started
> +  GL_ARB_derivative_control                            DONE (nv50, nvc0, r600)
>    GL_ARB_direct_state_access                           not started
>    GL_ARB_get_texture_sub_image                         started (Brian Paul)
>    GL_ARB_shader_texture_image_samples                  not started
> diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
> index 8a5ba79..bf52a19 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -305,6 +305,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
>         case PIPE_CAP_TEXTURE_GATHER_SM5:
>         case PIPE_CAP_TEXTURE_QUERY_LOD:
> +       case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
>                 return family >= CHIP_CEDAR ? 1 : 0;
>         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
>                 return family >= CHIP_CEDAR ? 4 : 0;
> @@ -319,7 +320,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
>         case PIPE_CAP_SAMPLE_SHADING:
>         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
>         case PIPE_CAP_DRAW_INDIRECT:
> -       case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
>                 return 0;
>
>         /* Stream output. */
> diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
> index e3407d5..5a6fa05 100644
> --- a/src/gallium/drivers/r600/r600_shader.c
> +++ b/src/gallium/drivers/r600/r600_shader.c
> @@ -5318,6 +5318,11 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
>         tex.src_gpr = src_gpr;
>         tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
>
> +       if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
> +               inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
> +               tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
> +       }
> +
>         if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
>                 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
>                 tex.inst_mod = texture_component_select;
> @@ -6906,6 +6911,11 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
>         {TGSI_OPCODE_LSB,       0, ALU_OP1_FFBL_INT, tgsi_unsupported},
>         {TGSI_OPCODE_IMSB,      0, ALU_OP1_FFBH_INT, tgsi_unsupported},
>         {TGSI_OPCODE_UMSB,      0, ALU_OP1_FFBH_UINT, tgsi_unsupported},
> +       {TGSI_OPCODE_INTERP_CENTROID,   0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_INTERP_SAMPLE,             0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_INTERP_OFFSET,             0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_DDX_FINE,  0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_DDY_FINE,  0, ALU_OP0_NOP, tgsi_unsupported},
>         {TGSI_OPCODE_LAST,      0, ALU_OP0_NOP, tgsi_unsupported},
>  };
>
> @@ -7109,6 +7119,11 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
>         {TGSI_OPCODE_LSB,       0, ALU_OP1_FFBL_INT, tgsi_op2},
>         {TGSI_OPCODE_IMSB,      0, ALU_OP1_FFBH_INT, tgsi_msb},
>         {TGSI_OPCODE_UMSB,      0, ALU_OP1_FFBH_UINT, tgsi_msb},
> +       {TGSI_OPCODE_INTERP_CENTROID,   0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_INTERP_SAMPLE,             0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_INTERP_OFFSET,             0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_DDX_FINE,  0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
> +       {TGSI_OPCODE_DDY_FINE,  0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
>         {TGSI_OPCODE_LAST,      0, ALU_OP0_NOP, tgsi_unsupported},
>  };
>
> @@ -7313,5 +7328,10 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
>         {TGSI_OPCODE_LSB,       0, ALU_OP1_FFBL_INT, tgsi_op2},
>         {TGSI_OPCODE_IMSB,      0, ALU_OP1_FFBH_INT, tgsi_msb},
>         {TGSI_OPCODE_UMSB,      0, ALU_OP1_FFBH_UINT, tgsi_msb},
> +       {TGSI_OPCODE_INTERP_CENTROID,   0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_INTERP_SAMPLE,             0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_INTERP_OFFSET,             0, ALU_OP0_NOP, tgsi_unsupported},
> +       {TGSI_OPCODE_DDX_FINE,  0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
> +       {TGSI_OPCODE_DDY_FINE,  0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
>         {TGSI_OPCODE_LAST,      0, ALU_OP0_NOP, tgsi_unsupported},
>  };
> --
> 1.8.3.2
>
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