[Mesa-dev] [PATCH] i965: Fix INTDIV math assertions on Broadwell.

[Kenneth Graunke]

Commit c66d928f2c9fa59e162c391fbdd37df969959718 ("i965: Enable INTDIV
in SIMD16 mode.") began using generate_math_gen6 to break SIMD16 INTDIV
into two SIMD8 operations.

generate_math_gen6 takes two registers - for unary operations, we pass
ARF null for the second operand.  Prior to Broadwell, real operands were
always GRF.  But now they can be IMM as well.

So, check for != ARF instead of == GRF.

+12 piglits.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 1190f1f..bbae418 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -304,7 +304,7 @@ fs_generator::generate_math_gen6(fs_inst *inst,
                                  struct brw_reg src1)
 {
    int op = brw_math_function(inst->opcode);
-   bool binop = src1.file == BRW_GENERAL_REGISTER_FILE;
+   bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
 
    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
    gen6_math(p, dst, op, src0, src1);
-- 
2.0.0