[Mesa-dev] [PATCH 01/17] i965/vec4/fs: Count loops in shader debug

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   | 6 ++++--
 src/mesa/drivers/dri/i965/brw_vec4.h             | 1 +
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 6 ++++--
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index a243003..c4e6c6d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1483,6 +1483,7 @@ void
 fs_generator::generate_code(exec_list *instructions)
 {
    int start_offset = p->next_insn_offset;
+   int loop_count = 0;
 
    struct annotation_info annotation;
    memset(&annotation, 0, sizeof(annotation));
@@ -1743,6 +1744,7 @@ fs_generator::generate_code(exec_list *instructions)
 
       case BRW_OPCODE_WHILE:
 	 brw_WHILE(p);
+         loop_count++;
 	 break;
 
       case SHADER_OPCODE_RCP:
@@ -1970,9 +1972,9 @@ fs_generator::generate_code(exec_list *instructions)
          fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
                  dispatch_width);
       }
-      fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
+      fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
                       " bytes (%.0f%%)\n",
-              dispatch_width, before_size / 16, before_size, after_size,
+              dispatch_width, before_size / 16, loop_count, before_size, after_size,
               100.0f * (before_size - after_size) / before_size);
 
       const struct gl_program *prog = fp ? &fp->Base : NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index c59d24f..c333baa 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -699,6 +699,7 @@ private:
 
    void *mem_ctx;
    const bool debug_flag;
+   int loop_count;
 };
 
 } /* namespace brw */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 1b1e647..b8948c3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1188,6 +1188,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
 
    case BRW_OPCODE_WHILE:
       brw_WHILE(p);
+      loop_count++;
       break;
 
    case SHADER_OPCODE_RCP:
@@ -1318,6 +1319,7 @@ vec4_generator::generate_code(exec_list *instructions)
 {
    struct annotation_info annotation;
    memset(&annotation, 0, sizeof(annotation));
+   loop_count = 0;
 
    cfg_t *cfg = NULL;
    if (unlikely(debug_flag))
@@ -1372,9 +1374,9 @@ vec4_generator::generate_code(exec_list *instructions)
       } else {
          fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
       }
-      fprintf(stderr, "vec4 shader: %d instructions. Compacted %d to %d"
+      fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
                       " bytes (%.0f%%)\n",
-              before_size / 16, before_size, after_size,
+              before_size / 16, loop_count, before_size, after_size,
               100.0f * (before_size - after_size) / before_size);
 
       dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
-- 
1.9.1