[Mesa-dev] [PATCH 2/7] r600g: use HTILE allocator from SI

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

It's almost the same.

This enables tiling for HTILE. It also enables Hyper-Z for other texture
targets (1D, 1D_ARRAY, 2D_ARRAY, CUBE, CUBE_ARRAY, 3D, RECT).

2D array depth textures are tested by Unigine Sanctuary and my new piglit
test.
---
 src/gallium/drivers/r600/evergreen_state.c |  5 +--
 src/gallium/drivers/r600/r600_state.c      |  5 +--
 src/gallium/drivers/radeon/r600_texture.c  | 60 ++++++++++--------------------
 3 files changed, 23 insertions(+), 47 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 73068ac..30cf32b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1266,9 +1266,8 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
 		uint64_t va = rtex->htile_buffer->gpu_address;
 		surf->db_htile_data_base = va >> 8;
 		surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
-					S_028ABC_HTILE_HEIGHT(1) |
-					S_028ABC_FULL_CACHE(1) |
-					S_028ABC_LINEAR(1);
+					 S_028ABC_HTILE_HEIGHT(1) |
+					 S_028ABC_FULL_CACHE(1);
 		surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
 		surf->db_preload_control = 0;
 	}
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 607b199..eb5d8f6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1104,9 +1104,8 @@ static void r600_init_depth_surface(struct r600_context *rctx,
 	if (rtex->htile_buffer && !level) {
 		surf->db_htile_data_base = 0;
 		surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
-					S_028D24_HTILE_HEIGHT(1) |
-					S_028D24_FULL_CACHE(1) |
-					S_028D24_LINEAR(1);
+					 S_028D24_HTILE_HEIGHT(1) |
+					 S_028D24_FULL_CACHE(1);
 		/* preload is not working properly on r6xx/r7xx */
 		surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
 	}
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index d07c9a0..17aca01 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -481,19 +481,34 @@ static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen
 		rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
 }
 
-static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
+static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
 					    struct r600_texture *rtex)
 {
 	unsigned cl_width, cl_height, width, height;
 	unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
 	unsigned num_pipes = rscreen->tiling_info.num_channels;
 
+	if (rscreen->chip_class <= EVERGREEN &&
+	    rscreen->info.drm_minor < 26)
+		return 0;
+
+	/* HW bug on R6xx. */
+	if (rscreen->chip_class == R600 &&
+	    (rtex->surface.level[0].npix_x > 7680 ||
+	     rtex->surface.level[0].npix_y > 7680))
+		return 0;
+
 	/* HTILE is broken with 1D tiling on old kernels and CIK. */
-	if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
-	    rscreen->chip_class >= CIK && rscreen->info.drm_minor < 38)
+	if (rscreen->chip_class >= CIK &&
+	    rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
+	    rscreen->info.drm_minor < 38)
 		return 0;
 
 	switch (num_pipes) {
+	case 1:
+		cl_width = 32;
+		cl_height = 16;
+		break;
 	case 2:
 		cl_width = 32;
 		cl_height = 32;
@@ -528,51 +543,14 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
 		align(slice_bytes, base_align);
 }
 
-static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
-					      struct r600_texture *rtex)
-{
-	unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
-	unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
-	unsigned npipes = rscreen->info.r600_num_tile_pipes;
-	unsigned htile_size;
-
-	/* XXX also use it for other texture targets */
-	if (rscreen->info.drm_minor < 26 ||
-	    rtex->resource.b.b.target != PIPE_TEXTURE_2D ||
-	    rtex->surface.level[0].nblk_x < 32 ||
-	    rtex->surface.level[0].nblk_y < 32) {
-		return 0;
-	}
-
-	/* HW bug on R6xx. */
-	if (rscreen->chip_class == R600 &&
-	    (rtex->surface.level[0].npix_x > 7680 ||
-	     rtex->surface.level[0].npix_y > 7680))
-		return 0;
-
-	/* this alignment and htile size only apply to linear htile buffer */
-	sw = align(sw, 16 << 3);
-	sh = align(sh, npipes << 3);
-	htile_size = (sw >> 3) * (sh >> 3) * 4;
-	/* must be aligned with 2K * npipes */
-	htile_size = align(htile_size, (2 << 10) * npipes);
-	return htile_size;
-}
-
 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
 					struct r600_texture *rtex)
 {
-	unsigned htile_size;
-	if (rscreen->chip_class >= SI) {
-		htile_size = si_texture_htile_alloc_size(rscreen, rtex);
-	} else {
-		htile_size = r600_texture_htile_alloc_size(rscreen, rtex);
-	}
+	unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
 
 	if (!htile_size)
 		return;
 
-	/* XXX don't allocate it separately */
 	rtex->htile_buffer = (struct r600_resource*)
 			     pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
 						PIPE_USAGE_DEFAULT, htile_size);
-- 
1.9.1