[Mesa-dev] [PATCH] radeonsi: set DB_DEPTH_SIZE.HEIGHT_TILE_MAX, inline other fields

[Michel Dänzer]

On 25.08.2014 19:13, Marek Olšák wrote:
> On Mon, Aug 25, 2014 at 9:15 AM, Michel Dänzer <michel at daenzer.net> wrote:
>> On 22.08.2014 00:51, Marek Olšák wrote:
>>>
>>> From: Marek Olšák <marek.olsak at amd.com>
>>>
>>> This fixes rendering to a non-zero layer/face/slice with HTILE.
>>>
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72685
>>
>>
>> [...]
>>
>>
>>> @@ -1782,12 +1783,6 @@ static void si_init_depth_surface(struct si_context
>>> *sctx,
>>>          z_offs += rtex->surface.level[level].offset;
>>>          s_offs += rtex->surface.stencil_level[level].offset;
>>>
>>> -       pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
>>> -       slice = (rtex->surface.level[level].nblk_x *
>>> rtex->surface.level[level].nblk_y) / 64;
>>> -       if (slice) {
>>> -               slice = slice - 1;
>>> -       }
>>> -
>>>          db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
>>>
>>>          z_info = S_028040_FORMAT(format);
>>> @@ -1876,8 +1871,10 @@ static void si_init_depth_surface(struct si_context
>>> *sctx,
>>>          surf->db_stencil_info = s_info;
>>>          surf->db_depth_base = z_offs >> 8;
>>>          surf->db_stencil_base = s_offs >> 8;
>>> -       surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
>>> -       surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
>>> +       surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x /
>>> 8) - 1) |
>>> +                             S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y
>>> / 8) - 1);
>>> +       surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x
>>> *
>>> +                                                       levelinfo->nblk_y)
>>> / 64 - 1);
>>
>>
>> if levelinfo->nblk_x * levelinfo->nblk_y < 64, this will set SLICE_TILE_MAX
>> to 0x3FFFFF instead of 0 as before. (Why) can't that happen, or isn't it a
>> problem?
>>
>> Though maybe it's better to just round up levelinfo->nblk_y to the next
>> multiple of 8 to avoid that; that might even prevent HEIGHT_TILE_MAX and
>> SLICE_TILE_MAX from getting programmed too low in more cases?
>
> DB only supports 1D and 2D tiling, which means the alignment is always
> at least 8x8. If a depth texture weren't aligned to 8x8, it wouldn't
> be possible to bind it as a depth buffer. Therefore we can assume
> nblk_x and nblk_y are multiples of 8 and nblk_x*nblk_y is a multiple
> 64.

I see. If you add assert()s that nblk_x and nblk_y are multiples of 8 
(in followup patches is fine), this patch and the corresponding r600g 
patch are

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>


-- 
Earthling Michel Dänzer            |                  http://www.amd.com
Libre software enthusiast          |                Mesa and X developer