[Mesa-dev] [PATCH] r600g, radeonsi: Inform the kernel if a BO will likely be accessed by the CPU

[Michel Dänzer]

From: Michel Dänzer <michel.daenzer at amd.com>

This allows the kernel to prevent such BOs from ever being stored in the
CPU inaccessible part of VRAM.

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
 src/gallium/drivers/radeon/r600_buffer_common.c | 23 ++++++++++++++---------
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c   |  8 +++++++-
 src/gallium/winsys/radeon/drm/radeon_winsys.h   |  3 ++-
 3 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index acdabc0..1a6e97d 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -126,6 +126,7 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
 			flags = RADEON_FLAG_GTT_WC;
 			break;
 		}
+		flags = RADEON_FLAG_CPU_ACCESS;
 		/* fall through */
 	case PIPE_USAGE_DEFAULT:
 	case PIPE_USAGE_IMMUTABLE:
@@ -136,23 +137,27 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
 		break;
 	}
 
-	/* Use GTT for all persistent mappings with older kernels, because they
-	 * didn't always flush the HDP cache before CS execution.
-	 *
-	 * Write-combined CPU mappings are fine, the kernel ensures all CPU
-	 * writes finish before the GPU executes a command stream.
-	 */
-	if (rscreen->info.drm_minor < 40 &&
-	    res->b.b.target == PIPE_BUFFER &&
+	if (res->b.b.target == PIPE_BUFFER &&
 	    res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 			      PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
-		res->domains = RADEON_DOMAIN_GTT;
+		/* Use GTT for all persistent mappings with older kernels,
+		 * because they didn't always flush the HDP cache before CS
+		 * execution.
+		 *
+		 * Write-combined CPU mappings are fine, the kernel ensures all CPU
+		 * writes finish before the GPU executes a command stream.
+		 */
+		if (rscreen->info.drm_minor < 40)
+			res->domains = RADEON_DOMAIN_GTT;
+		else if (res->domains & RADEON_DOMAIN_VRAM)
+			flags |= RADEON_FLAG_CPU_ACCESS;
 	}
 
 	/* Tiled textures are unmappable. Always put them in VRAM. */
 	if (res->b.b.target != PIPE_BUFFER &&
 	    rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
 		res->domains = RADEON_DOMAIN_VRAM;
+		flags &= ~RADEON_FLAG_CPU_ACCESS;
 	}
 
 	/* Allocate a new resource. */
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 73f8d38..03b9b1d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -478,7 +478,11 @@ const struct pb_vtbl radeon_bo_vtbl = {
 };
 
 #ifndef RADEON_GEM_GTT_WC
-#define RADEON_GEM_GTT_WC (1 << 2)
+#define RADEON_GEM_GTT_WC	(1 << 2)
+#endif
+#ifndef RADEON_GTM_CPU_ACCESS
+/* BO is expected to be accessed by the CPU */
+#define RADEON_GEM_CPU_ACCESS	(1 << 3)
 #endif
 
 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
@@ -505,6 +509,8 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
 
     if (rdesc->flags & RADEON_FLAG_GTT_WC)
         args.flags |= RADEON_GEM_GTT_WC;
+    if (rdesc->flags & RADEON_FLAG_CPU_ACCESS)
+        args.flags |= RADEON_GEM_CPU_ACCESS;
 
     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
                             &args, sizeof(args))) {
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index dbd58f1..69bf6ed 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -66,7 +66,8 @@ enum radeon_bo_domain { /* bitfield */
 };
 
 enum radeon_bo_flag { /* bitfield */
-   RADEON_FLAG_GTT_WC = (1 << 0)
+    RADEON_FLAG_GTT_WC =     (1 << 0),
+    RADEON_FLAG_CPU_ACCESS = (1 << 1),
 };
 
 enum radeon_bo_usage { /* bitfield */
-- 
2.1.0