[Mesa-dev] [PATCH 1/4] i965/byt: Allow 128 bpp to be linear or Y-tiled on

[Daniel Vetter]

On Tue, Dec 09, 2014 at 04:02:57PM -0800, Ben Widawsky wrote:
> Let's assume that this IVB specific feature exists on BYT too, since it's very
> much like IVB
> 
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 7081f1d..4ae700c 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -490,7 +490,7 @@ intel_miptree_choose_tiling(struct brw_context *brw,
>      * 128 bits per pixel translates to 16 bytes per pixel.  This is necessary
>      * all the way back to 965, but is explicitly permitted on Gen7.
>      */
> -   if (brw->gen != 7 && mt->cpp >= 16)
> +   if ((brw->gen != 7 && !brw->is_baytrail) && mt->cpp >= 16)

gen == 7 already implies is_baytrail if I read the mesa device tables
correctly, so looks redundant?
-Daniel

>        return I915_TILING_X;
>  
>     /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
> -- 
> 2.1.3
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch