[Mesa-dev] [PATCH] radeonsi: implement legacy RCP behavior to fix Unreal engine demos

[Roland Scheidegger]

Hmm so would that apply to all vector alu ops? Weird (dx10 certainly
does not generally clamp NaNs to zero).

Roland

Am 10.12.2014 um 21:40 schrieb Marek Olšák:
> From the SI ISA:
> 
> "Used by the vector ALU to force DX10-style treatment of NaNs: when
> set, clamp NaN to zero; otherwise, pass NaN through."
> 
> Marek
> 
> On Wed, Dec 10, 2014 at 9:33 PM, Roland Scheidegger <sroland at vmware.com> wrote:
>> I am curious, how does this bit change the shader (or shader operations,
>> export, or whatever).
>> I guess you're referring to the bit saying "Drives dx10 clamp in spi_sq
>> newWave cmd" settable separately for each shader type but that doesn't
>> mean much to me :-).
>>
>> Roland
>>
>> Am 10.12.2014 um 21:16 schrieb Marek Olšák:
>>> Wow, yes! The DX10_CLAMP bit fixes this issue too. I guess we don't
>>> have to use legacy instructions now.
>>>
>>> Marek
>>>
>>> On Mon, Dec 8, 2014 at 5:05 AM, Michel Dänzer <michel at daenzer.net> wrote:
>>>> On 04.12.2014 21:34, Marek Olšák wrote:
>>>>> From: Marek Olšák <marek.olsak at amd.com>
>>>>>
>>>>> Discussion: https://urldefense.proofpoint.com/v2/url?u=https-3A__bugs.freedesktop.org_show-5Fbug.cgi-3Fid-3D83510-23c8&d=AAIGaQ&c=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw-YihVMNtXt-uEs&r=Vjtt0vs_iqoI31UfJxBl7yv9I2FeiaeAYgMTLKRBc_I&m=wYbokNJOnFBGstvWMmYoGPCVEP9QfPQw0wnRl42Jw0Q&s=rVzVSrX2MYZiMDzqraJyiS53MdcsrSnVfVdG6WQyWOs&e=
>>>>
>>>> I wonder if we could avoid at least some of this trouble using the DX10
>>>> / IEEE bits in the shader MODE register.
>>>>
>>>>
>>>> --
>>>> Earthling Michel Dänzer               |               https://urldefense.proofpoint.com/v2/url?u=http-3A__www.amd.com_&d=AAIGaQ&c=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw-YihVMNtXt-uEs&r=Vjtt0vs_iqoI31UfJxBl7yv9I2FeiaeAYgMTLKRBc_I&m=wYbokNJOnFBGstvWMmYoGPCVEP9QfPQw0wnRl42Jw0Q&s=j8yXvz073rSQDrLT-gDX9jMI3wFgZNH4XNK78KVjwF4&e=
>>>> Libre software enthusiast             |             Mesa and X developer
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>>