[Mesa-dev] [PATCH] i965: Cache register write capability checks.

[Ben Widawsky]

On Mon, Dec 22, 2014 at 01:28:32AM -0800, Kenneth Graunke wrote:
> Our ability to perform register writes depends on the hardware and
> kernel version.  It shouldn't ever change on a per-context basis,
> so we only need to check once.

That's actually not true. The kernel currently supports dynamic changes of the
module parameter for the command parser. Because of that, and the fact that this
improves one very synthetic microbench, in a perfect world we'd not merge this
patch. However, I live in the real world, so maybe just add a comment that you
can potentially shoot yourself in the foot if you change the module parameter in
a running system, and then it's

Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

>  
> Checking introduces a synchronization point between the CPU and GPU:
> even though we submit very few GPU commands, the GPU might be busy doing
> other work, which could cause us to stall for a while.
> 
> On an idle i7 4750HQ, this improves performance in OglDrvCtx (a context
> creation microbenchmark) by 6.14748% +/- 1.6837% (n=20).  With Unigine
> Valley running in the background (to keep the GPU busy), it improves
> performance in OglDrvCtx by 2290.92% +/- 29.5274% (n=5).
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/intel_extensions.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
> index bbbb76f..3cbfaaf 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -46,6 +46,10 @@ can_do_pipelined_register_writes(struct brw_context *brw)
>     if (brw->gen >= 8)
>        return true;
>  
> +   static int result = -1;
> +   if (result != -1)
> +      return result;
> +
>     /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
>      * statistics registers), and we already reset it to zero before using it.
>      */
> @@ -91,6 +95,8 @@ can_do_pipelined_register_writes(struct brw_context *brw)
>     bool success = data[offset] == expected_value;
>     drm_intel_bo_unmap(brw->batch.workaround_bo);
>  
> +   result = success;
> +
>     return success;
>  }
>  
> @@ -100,6 +106,10 @@ can_write_oacontrol(struct brw_context *brw)
>     if (brw->gen < 6 || brw->gen >= 8)
>        return false;
>  
> +   static int result = -1;
> +   if (result != -1)
> +      return result;
> +
>     /* Set "Select Context ID" to a particular address (which is likely not a
>      * context), but leave all counting disabled.  This should be harmless.
>      */
> @@ -150,6 +160,8 @@ can_write_oacontrol(struct brw_context *brw)
>     bool success = data[offset] == expected_value;
>     drm_intel_bo_unmap(brw->batch.workaround_bo);
>  
> +   result = success;
> +
>     return success;
>  }
>  
> -- 
> 2.2.1
> 
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-- 
Ben Widawsky, Intel Open Source Technology Center