[Mesa-dev] [PATCH v3] R600/SI: Fix fneg for 0.0

Tom Stellard tom at stellard.net
Tue Feb 4 07:10:53 CET 2014 

On Tue, Feb 04, 2014 at 01:18:24PM +0900, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
> 
> V_ADD_F32 with source modifier does not produce -0.0 for this. Just
> manipulate the sign bit directly instead.
> 
> Also add a pattern for (fneg (fabs ...)).
> 
> Fixes a bunch of bit encoding piglit tests with radeonsi.
> 
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> ---
> 
> v3: Add explanatory comments.
> 
>  lib/Target/R600/SIInstructions.td | 22 +++++++++++++---
>  test/CodeGen/R600/fabs.ll         | 14 +++++-----
>  test/CodeGen/R600/fneg-fabs.ll    | 55 +++++++++++++++++++++++++++++++++++++++
>  test/CodeGen/R600/fneg.ll         | 14 +++++-----
>  4 files changed, 87 insertions(+), 18 deletions(-)
>  create mode 100644 test/CodeGen/R600/fneg-fabs.ll
> 
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index b9e0c17..25fd7d5 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -1688,16 +1688,30 @@ def : Pat <
>     0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
>  >;
>  
> +/********** ================================ **********/
> +/********** Floating point absolute/negative **********/
> +/********** ================================ **********/
> +
> +// Manipulate the sign bit directly, as e.g. using the source negation modifier
> +// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0,
> +// breaking the piglit *s-floatBitsToInt-neg* tests
> +
> +// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
> +// removing these patterns
> +
> +def : Pat <
> +  (fneg (fabs f32:$src)),
> +  (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
> +>;
> +
>  def : Pat <
>    (fabs f32:$src),
> -  (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
> -   1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
> +  (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */
>  >;
>  
>  def : Pat <
>    (fneg f32:$src),
> -  (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
> -   0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
> +  (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */
>  >;
>  
>  /********** ================== **********/
> diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll
> index a5f5df9..2cd3a4f 100644
> --- a/test/CodeGen/R600/fabs.ll
> +++ b/test/CodeGen/R600/fabs.ll
> @@ -9,7 +9,7 @@
>  ; R600-CHECK-NOT: AND
>  ; R600-CHECK: |PV.{{[XYZW]}}|
>  ; SI-CHECK-LABEL: @fabs_free
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_AND_B32
>  
>  define void @fabs_free(float addrspace(1)* %out, i32 %in) {
>  entry:
> @@ -23,8 +23,8 @@ entry:
>  ; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
>  ; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
>  ; SI-CHECK-LABEL: @fabs_v2
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_AND_B32
> +; SI-CHECK: V_AND_B32
>  define void @fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
>  entry:
>    %0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
> @@ -38,10 +38,10 @@ entry:
>  ; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
>  ; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
>  ; SI-CHECK-LABEL: @fabs_v4
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0
> +; SI-CHECK: V_AND_B32
> +; SI-CHECK: V_AND_B32
> +; SI-CHECK: V_AND_B32
> +; SI-CHECK: V_AND_B32
>  define void @fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
>  entry:
>    %0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
> diff --git a/test/CodeGen/R600/fneg-fabs.ll b/test/CodeGen/R600/fneg-fabs.ll
> new file mode 100644
> index 0000000..d95e131
> --- /dev/null
> +++ b/test/CodeGen/R600/fneg-fabs.ll
> @@ -0,0 +1,55 @@
> +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
> +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
> +
> +; DAGCombiner will transform:
> +; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
> +; unless isFabsFree returns true
> +
> +; R600-CHECK-LABEL: @fneg_fabs_free
> +; R600-CHECK-NOT: AND
> +; R600-CHECK: |PV.{{[XYZW]}}|
> +; R600-CHECK: -PV
> +; SI-CHECK-LABEL: @fneg_fabs_free
> +; SI-CHECK: V_OR_B32
> +
> +define void @fneg_fabs_free(float addrspace(1)* %out, i32 %in) {
> +entry:
> +  %0 = bitcast i32 %in to float
> +  %1 = call float @fabs(float %0)
> +  %2 = fsub float -0.000000e+00, %1
> +  store float %2, float addrspace(1)* %out
> +  ret void
> +}
> +
> +; R600-CHECK-LABEL: @fneg_fabs_v2
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; R600-CHECK: -PV
> +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}|
> +; R600-CHECK: -PV
> +; SI-CHECK-LABEL: @fneg_fabs_v2
> +; SI-CHECK: V_OR_B32
> +; SI-CHECK: V_OR_B32
> +define void @fneg_fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
> +entry:
> +  %0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
> +  %1 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %0
> +  store <2 x float> %1, <2 x float> addrspace(1)* %out
> +  ret void
> +}
> +
> +; SI-CHECK-LABEL: @fneg_fabs_v4
> +; SI-CHECK: V_OR_B32
> +; SI-CHECK: V_OR_B32
> +; SI-CHECK: V_OR_B32
> +; SI-CHECK: V_OR_B32
> +define void @fneg_fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
> +entry:
> +  %0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
> +  %1 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %0
> +  store <4 x float> %1, <4 x float> addrspace(1)* %out
> +  ret void
> +}
> +
> +declare float @fabs(float ) readnone
> +declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone
> +declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone
> diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll
> index 9446aa8..f4e6be6 100644
> --- a/test/CodeGen/R600/fneg.ll
> +++ b/test/CodeGen/R600/fneg.ll
> @@ -4,7 +4,7 @@
>  ; R600-CHECK-LABEL: @fneg
>  ; R600-CHECK: -PV
>  ; SI-CHECK-LABEL: @fneg
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
> +; SI-CHECK: V_XOR_B32
>  define void @fneg(float addrspace(1)* %out, float %in) {
>  entry:
>    %0 = fsub float -0.000000e+00, %in
> @@ -16,8 +16,8 @@ entry:
>  ; R600-CHECK: -PV
>  ; R600-CHECK: -PV
>  ; SI-CHECK-LABEL: @fneg_v2
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
> +; SI-CHECK: V_XOR_B32
> +; SI-CHECK: V_XOR_B32
>  define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
>  entry:
>    %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
> @@ -31,10 +31,10 @@ entry:
>  ; R600-CHECK: -PV
>  ; R600-CHECK: -PV
>  ; SI-CHECK-LABEL: @fneg_v4
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
> -; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1
> +; SI-CHECK: V_XOR_B32
> +; SI-CHECK: V_XOR_B32
> +; SI-CHECK: V_XOR_B32
> +; SI-CHECK: V_XOR_B32
>  define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
>  entry:
>    %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
> -- 
> 1.9.rc1
> 
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