[Mesa-dev] Blorp without surface state xy-offsets
Topi Pohjolainen
topi.pohjolainen at intel.com
Mon Feb 10 11:53:08 PST 2014
Surface state for blorp handles miplevel (and layer) offsets by
adding full pages to the base address and the remaining offset
within a tile (page) using special tile_xy-fields in the surface
state config.
This series moves the intra-tile offset handling to the blorp
program. Vertices provided to the hardware are adjusted along
with the drawing rectangle, and sampling offsets are shifted to
compensate for the destination shift as well as to any offset
in the source surface itself. This is all Paul's idea - I just
tried to it implement accordingly.
Originally the idea was to use hardware support for miplevel
and layer access. This is proved to be very difficult due to the
need for treating w-tiled stencil as y-tiled. Once miplevels
become small enough, the aspect ratio changes between Y and
W requiring special adjusting in the blorp program.
The chosen approach should be a lot safer.
I haven't tried yet but I cannot see any reason why the hardware
layer support couldn't be enabled on top of this.
Topi Pohjolainen (7):
i965/blorp: refactor assertions for tile offset alignments
i965/blorp: split calculations of page and tile offsets
i965/blorp: add intra-tile offset support without surface config
i965/blorp: handle destination tile offsets for w-tiled in the program
i965/blorp: handle source tile offsets for w-tiled in the program
i965/blorp: handle tile offsets for all destinations in the program
i965/blorp: handle tile offsets for all sources in the program
src/mesa/drivers/dri/i965/brw_blorp.cpp | 87 +++++++++++++++++++++++++--
src/mesa/drivers/dri/i965/brw_blorp.h | 21 ++++++-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 5 ++
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 45 ++++++++------
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 18 +++---
6 files changed, 143 insertions(+), 35 deletions(-)
--
1.8.3.1
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