[Mesa-dev] [PATCH 1/2] i965/fs: Simplify FS_OPCODE_SET_SAMPLE_ID stride mashing a bit.

[Ian Romanick]

Series is

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>

On 02/10/2014 03:46 PM, Kenneth Graunke wrote:
> stride(brw_vec1_reg(...) ...) takes some register, changes the strides,
> then changes the strides again.  Let's do it once.
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 6d211e1..26913d2 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -1156,8 +1156,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
>     brw_push_insn_state(p);
>     brw_set_compression_control(p, BRW_COMPRESSION_NONE);
>     brw_set_mask_control(p, BRW_MASK_DISABLE);
> -   struct brw_reg reg = stride(retype(brw_vec1_reg(src1.file, src1.nr, 0),
> -                                      BRW_REGISTER_TYPE_UW), 1, 4, 0);
> +   struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
>     brw_ADD(p, dst, src0, reg);
>     if (dispatch_width == 16)
>        brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
>