[Mesa-dev] [PATCH 1/4] r600/video: disable tilling for now v2

[Christian König]

From: Christian König <christian.koenig at amd.com>

v2: cleanup, add some comments

Signed-off-by: Christian König <christian.koenig at amd.com>
---
 src/gallium/drivers/r600/r600_uvd.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c
index f42384c..f5596da 100644
--- a/src/gallium/drivers/r600/r600_uvd.c
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -49,6 +49,9 @@
 #include "radeon/radeon_uvd.h"
 #include "r600d.h"
 
+/* Tilling only works with UVD but not VCE, disable it for now */
+#define ENABLE_TILLING 0
+
 /**
  * creates an video buffer with an UVD compatible memory layout
  */
@@ -77,7 +80,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
 	template.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
 
 	vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_DEFAULT, 0);
-	if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced)
+	if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !ENABLE_TILLING)
 		templ.bind = PIPE_BIND_LINEAR;
 	resources[0] = (struct r600_texture *)
 		pipe->screen->resource_create(pipe->screen, &templ);
@@ -86,7 +89,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
 
 	if (resource_formats[1] != PIPE_FORMAT_NONE) {
 		vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_DEFAULT, 1);
-		if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced)
+		if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !ENABLE_TILLING)
 			templ.bind = PIPE_BIND_LINEAR;
 		resources[1] = (struct r600_texture *)
 			pipe->screen->resource_create(pipe->screen, &templ);
@@ -96,7 +99,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
 
 	if (resource_formats[2] != PIPE_FORMAT_NONE) {
 		vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_DEFAULT, 2);
-		if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced)
+		if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !ENABLE_TILLING)
 			templ.bind = PIPE_BIND_LINEAR;
 		resources[2] = (struct r600_texture *)
 			pipe->screen->resource_create(pipe->screen, &templ);
-- 
1.8.3.2