[Mesa-dev] [RFC] ARB_stencil_texturing on Gen6/7
Pohjolainen, Topi
topi.pohjolainen at intel.com
Sat Feb 22 08:49:23 PST 2014
On Sat, Feb 22, 2014 at 11:05:26AM +0200, Topi Pohjolainen wrote:
> This series adda stencil texturing support for gen6 and gen7. It's tested
> against regression on IVB and SNB. Both also pass the piglit tests we have
> for fragment shaders with texture() and texelFetch().
And forgot to add that the stencil texture tests also pass with
INTEL_DEBUG=no16 and that the tree is available at:
git://people.freedesktop.org/~tpohjola/mesa:stencil-texture
>
> First three patches are just general cleanups/improvements I found along
> the way.
>
> Patches 4-7 add the option to offset a texture surface directly to the
> desired miplevel. This will use both the page offset and xy-tile offsets.
> Patch 8 starts to use this in addition to lying to the hardware about
> W-tiled stencil buffers - they will be set in blorp style as Y-tiled and
> with adjusted dimensions.
>
> Patches 9-20 are quite intrusive - they merge some of the duplicated logic
> between fs and vec4 ir-visitors and split them in two parts: visitors and
> emitters. There is still quite a bit of pure LIR-emission logic left in
> fs_visitor. I only moved as much as was needed for blorp blitter for now.
>
> before after
> ------ -----
>
> backend_visitor backend_visitor backend_emitter
> | | |
> / \ / \ / \
> | | |
> +------+------+ +------+------+ +------+------+
> | | | | | |
> vec4_visitor fs_visitor | vec4_visitor fs_emitter
> | |
> | / \
> | |
> | +------+------+
> | | |
> +------------+-----------+ brw_blorp_eu_emitter
> |
> fs_visitor
>
> Patch 21 then shares the blorp code that emits LIR for translating coordinates
> in W-tiled layout into coordinates that describe the same byte in linear memory
> but in Y-tiled layout.
>
> In order to translate between W and Y-layouts, however, one needs to have
> unnormalized coordinates. Patches 22,23 add the support for emitting
> instructions that ask the texture dimensions from hardware. Patch 25 combines
> 22,23 and the de/normalizing support of 24 into emission of W-to-Y translation
> for W-tiled stencil targets.
> Patch 26 adds the control when the translation is needed in runtime and finally
> 27 enables the whole thing - this is premature of course as the equivalent
> vertex logic is still missing.
>
> Topi Pohjolainen (27):
> i965: Remove unused sampler key fields
> i965: Mark sources for offset getters as constants
> i965/vec4: Mark invariant members as constants in vec4_visitor
> i965: Allow w-tiled miptree offsets to be resolved as y-tiled directly
> i965/wm: Use resolved miptree consistently in surface setup
> i965/wm: Refactor resolving of texture parameters
> i965/wm: Introduce support for texture surface x/y-tile offsets
> i965/fs: Configure w-tiled stencil surfaces as y-tiled on gen6/7
> i965: Merge initialisation of backend_visitor
> i965: Merge resolving of shader program source
> i965: Mark invariants in backend_visitor as constants
> i965: Split emitter out of backend_visitor
> i965: Merge memory context allocation for shader visitors
> i965: Merge max_grf between stage compilers
> i965/vec4: Use unsigned instead of signed for visitor uniform count
> i965: Merge common members of visitors
> i965: Merge fail() for ir visitors
> i965/fs: Split LIR emission ouf of ir-visitor
> i965/fs: Move emission of ALUs into fs_emitter
> i965/blorp: Use fs_emitter
> i965/blorp: Refactor w-tiling to y-tiling translation
> i965/fs: Add generator support for fetching texture dimensions
> i965/fs: Add helper for emitting plain texture resinfo messages
> i965/fs: Add helpers for de/normalizing values
> i965/fs: Emit coordinate translation from W to Y-tiling
> i965/fs: Recompile when switching to/from stencil indexing
> i965: Enable ARB_stencil_texturing on Gen6.
>
> src/mesa/drivers/dri/i965/Makefile.sources | 1 +
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 331 ++++++++++-----------
> src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 28 +-
> src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 110 +------
> src/mesa/drivers/dri/i965/brw_cfg.cpp | 8 +-
> src/mesa/drivers/dri/i965/brw_cfg.h | 4 +-
> .../drivers/dri/i965/brw_dead_control_flow.cpp | 6 +-
> src/mesa/drivers/dri/i965/brw_dead_control_flow.h | 2 +-
> src/mesa/drivers/dri/i965/brw_defines.h | 2 +
> src/mesa/drivers/dri/i965/brw_fs.cpp | 157 +---------
> src/mesa/drivers/dri/i965/brw_fs.h | 161 +++++-----
> src/mesa/drivers/dri/i965/brw_fs_emitter.cpp | 317 ++++++++++++++++++++
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 33 ++
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 202 ++++++++-----
> src/mesa/drivers/dri/i965/brw_program.h | 13 +-
> .../drivers/dri/i965/brw_schedule_instructions.cpp | 4 +-
> src/mesa/drivers/dri/i965/brw_shader.cpp | 72 ++++-
> src/mesa/drivers/dri/i965/brw_shader.h | 74 ++++-
> src/mesa/drivers/dri/i965/brw_state.h | 23 ++
> src/mesa/drivers/dri/i965/brw_vec4.cpp | 14 +-
> src/mesa/drivers/dri/i965/brw_vec4.h | 36 +--
> src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 14 +-
> src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h | 2 -
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 72 +----
> src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 9 +-
> src/mesa/drivers/dri/i965/brw_vs.h | 4 +-
> src/mesa/drivers/dri/i965/brw_wm.c | 17 +-
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 92 +++++-
> src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 33 +-
> src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
> src/mesa/drivers/dri/i965/intel_fbo.h | 2 +-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 +-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 +-
> src/mesa/drivers/dri/i965/intel_regions.c | 4 +-
> src/mesa/drivers/dri/i965/intel_regions.h | 4 +-
> src/mesa/drivers/dri/i965/intel_tex_image.c | 3 +-
> .../dri/i965/test_vec4_register_coalesce.cpp | 3 +-
> 39 files changed, 1083 insertions(+), 802 deletions(-)
> create mode 100644 src/mesa/drivers/dri/i965/brw_fs_emitter.cpp
>
> --
> 1.8.3.1
>
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