[Mesa-dev] [PATCH 05/10] i965: Use Global GTT for Sandybridge post-sync non-zero workaround.

[Eric Anholt]

Kenneth Graunke <kenneth at whitecape.org> writes:

> On 01/09/2014 10:03 PM, Eric Anholt wrote:
>> Eric Anholt <eric at anholt.net> writes:
>> 
>>> Kenneth Graunke <kenneth at whitecape.org> writes:
>>>
>>>> The kernel doesn't even set up the aliasing PPGTT on Sandybridge, so any
>>>> writes marked as PPGTT will likely just get dropped on the floor.
>>>
>>> The hardware bug is that writes not marked as GTT are still looked up in
>>> the GTT anyway.
>>>
>>> The kernel does set up the PPGTT, which is how we found we needed to put
>>> in the kernel workaround based on DOMAIN_INSTRUCTION (of binding the
>>> target buffer to the gtt as well as the ppgtt, since the writes landed
>>> in the wrong place)
>>>
>>> I don't think this patch will change anything, but it seems reasonable
>>> if the commit message is updated.
>> 
>> Actually, thinking about it more, I'd rather not explicitly use global
>> GTT, unless the function is also renamed to
>> gen6_emit_post_sync_nonzero_workaround, since now this function on
>> non-gen6 would reference GTT memory in its instruction, but the kernel
>> wouldn't put anything in the GTT.
>> 
>> (I'd rather just leave the workaround as is, myself).
>
> Okay, sounds like this is unnecessary.  But...the next patch (helper
> function for writes) causes this to use PIPE_CONTROL_GLOBAL_GTT_WRITE on
> SNB only, and PPGTT on Gen7+.

Oh, right.  I'm fine with this as-is, then (r-b).
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