[Mesa-dev] [v2 07/23] i965/blorp: move emission of sample combining into eu-emitter

[Topi Pohjolainen]

v2 (Paul): pass the combining opcode as an argument to emit_combine().
           This keeps manual_blend_average() selfcontained
           documentation wise.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Paul Berry <stereotype441 at gmail.com> (v1)
---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp    | 14 +++++---------
 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 14 ++++++++++++++
 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h   |  5 +++++
 3 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 4bbdf3d..b5f1907 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1534,12 +1534,6 @@ brw_blorp_blit_program::manual_blend_average(unsigned num_samples)
     * For integer formats, we replace the add operations with average
     * operations and skip the final division.
     */
-   typedef struct brw_instruction *(*brw_op2_ptr)(struct brw_compile *,
-                                                  struct brw_reg,
-                                                  struct brw_reg,
-                                                  struct brw_reg);
-   brw_op2_ptr combine_op =
-      key->texture_data_type == BRW_REGISTER_TYPE_F ? brw_ADD : brw_AVG;
    unsigned stack_depth = 0;
    for (unsigned i = 0; i < num_samples; ++i) {
       assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */
@@ -1581,9 +1575,11 @@ brw_blorp_blit_program::manual_blend_average(unsigned num_samples)
 
          /* TODO: should use a smaller loop bound for non_RGBA formats */
          for (int k = 0; k < 4; ++k) {
-            combine_op(&func, offset(texture_data[stack_depth - 1], 2*k),
-                       offset(vec8(texture_data[stack_depth - 1]), 2*k),
-                       offset(vec8(texture_data[stack_depth]), 2*k));
+            emit_combine(key->texture_data_type == BRW_REGISTER_TYPE_F ?
+                            BRW_OPCODE_ADD : BRW_OPCODE_AVG,
+                         offset(texture_data[stack_depth - 1], 2*k),
+                         offset(vec8(texture_data[stack_depth - 1]), 2*k),
+                         offset(vec8(texture_data[stack_depth]), 2*k));
          }
       }
    }
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index df8d63d..9b63458 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -152,3 +152,17 @@ brw_blorp_eu_emitter::emit_render_target_write(const struct brw_reg &src0,
                 true /* eot */,
                 use_header);
 }
+
+void
+brw_blorp_eu_emitter::emit_combine(enum opcode combine_opcode,
+                                   const struct brw_reg &dst,
+                                   const struct brw_reg &src_1,
+                                   const struct brw_reg &src_2)
+{
+   assert(combine_opcode == BRW_OPCODE_ADD || combine_opcode == BRW_OPCODE_AVG);
+
+   if (combine_opcode == BRW_OPCODE_ADD)
+      brw_ADD(&func, dst, src_1, src_2);
+   else
+      brw_AVG(&func, dst, src_1, src_2);
+}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index 5f0c8cf..55e05f7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -52,6 +52,11 @@ protected:
                                  unsigned msg_length,
                                  bool use_header);
 
+   void emit_combine(enum opcode combine_opcode,
+                     const struct brw_reg &dst,
+                     const struct brw_reg &src_1,
+                     const struct brw_reg &src_2);
+
    void *mem_ctx;
    struct brw_compile func;
 };
-- 
1.8.3.1