[Mesa-dev] [RFC PATCH 13/16] i965: Support array_spacing_lod0 for multiple miplevels

[Pohjolainen, Topi]

On Thu, May 29, 2014 at 01:53:52PM -0700, Jordan Justen wrote:
> Previously array spacing lod0 was only used with a single mip level.
> 
> It indicated that no mip level spacing should be used between array
> slices.
> 
> gen6 stencil only support LOD0, so we need to allocate the miptree
> similar to array spacing lod0, except we also need space for more
> than just one mip level.
> 
> So, the miptree is allocated with tightly packed array slice spacing,
> but we still also pack the miplevels into the region similar to a
> normal multi mip level packing.
> 
> Essentially, the miptree is set up as if the texture slices formed
> one tall 2D texture, rather than a 2D array.

I'm also thinking that wouldn't it be clearer to have new flag for this
instead of extending the semantics for 'array_spacing_lod0'. From gen7 onwards
this is specifically used to configure the surfaces for optimized layout but
not on gen6 yet. Now on gen6 it would used to signal special layout of layered
miptrees instead, and for stencil only.

> 
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_tex_layout.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 76044b2..8a0912d 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -203,6 +203,11 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
>        if (mt->compressed)
>  	 img_height /= mt->align_h;
>  
> +      if (mt->array_spacing_lod0) {
> +         /* Compact arrays with separated miplevels */
> +	 img_height *= depth;
> +      }
> +
>        /* Because the images are packed better, the final offset
>         * might not be the maximal one:
>         */
> @@ -238,6 +243,7 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
>  				 struct intel_mipmap_tree *mt)
>  {
>     int h0, h1;
> +   unsigned height = mt->physical_height0;
>  
>     h0 = ALIGN(mt->physical_height0, mt->align_h);
>     h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
> @@ -251,11 +257,22 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
>     brw_miptree_layout_2d(mt);
>  
>     for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
> +      unsigned img_height;
> +      img_height = ALIGN(height, mt->align_h);
> +      if (mt->compressed)
> +         img_height /= mt->align_h;
> +
>        for (int q = 0; q < mt->physical_depth0; q++) {
> -	 intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
> +         if (mt->array_spacing_lod0) {
> +            intel_miptree_set_image_offset(mt, level, q, 0, q * img_height);
> +         } else {
> +            intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
> +         }
>        }
> +      height = minify(height, 1);
>     }
> -   mt->total_height = physical_qpitch * mt->physical_depth0;
> +   if (!mt->array_spacing_lod0)
> +      mt->total_height = physical_qpitch * mt->physical_depth0;
>  
>     align_cube(mt);
>  }
> -- 
> 2.0.0.rc4
> 
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