[Mesa-dev] [PATCH 1/3] i965/gen7: Refactor renderbuffer target override
Topi Pohjolainen
topi.pohjolainen at intel.com
Mon Jun 2 03:14:21 PDT 2014
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_state.h | 8 ++++++++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 17 +++++++++++++++++
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 4 +---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 8 ++------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 8 ++------
5 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index dbcf7c7..ee87092 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -202,8 +202,16 @@ void *brw_state_batch(struct brw_context *brw,
uint32_t *out_offset);
/* brw_wm_surface_state.c */
+
+inline static GLenum
+brw_get_target(const struct gl_renderbuffer *rb)
+{
+ return rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
+}
+
void gen4_init_vtable_surface_functions(struct brw_context *brw);
uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
+uint32_t brw_get_surface_type(GLenum gl_target);
uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
void brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c9d9614..4cc3f49 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -91,6 +91,23 @@ brw_get_surface_tiling_bits(uint32_t tiling)
}
}
+uint32_t
+brw_get_surface_type(const GLenum gl_target)
+{
+ switch (gl_target) {
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_CUBE_MAP:
+ /* The PRM claims that we should use BRW_SURFACE_CUBE for this
+ * situation, but experiments show that gl_Layer doesn't work when we do
+ * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
+ * equivalent.
+ */
+ return BRW_SURFACE_2D;
+ case GL_TEXTURE_3D:
+ default:
+ return translate_tex_target(gl_target);
+ }
+}
uint32_t
brw_get_surface_num_multisamples(unsigned num_samples)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 448b505..74c2ca3 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -684,10 +684,10 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
{
const uint8_t mocs = GEN7_MOCS_L3;
uint32_t surfwidth, surfheight;
- uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
unsigned int min_array_element;
GLenum gl_target = params->depth.mt->target;
+ const uint32_t surftype = brw_get_surface_type(gl_target);
unsigned int lod;
switch (gl_target) {
@@ -698,11 +698,9 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
* this. So we use BRW_SURFACE_2D, since for rendering purposes this is
* equivalent.
*/
- surftype = BRW_SURFACE_2D;
depth *= 6;
break;
default:
- surftype = translate_tex_target(gl_target);
break;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 22911bf..870e2c7 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -42,10 +42,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
struct gl_context *ctx = &brw->ctx;
const uint8_t mocs = GEN7_MOCS_L3;
struct gl_framebuffer *fb = ctx->DrawBuffer;
- uint32_t surftype;
unsigned int depth = 1;
unsigned int min_array_element;
- GLenum gl_target = GL_TEXTURE_2D;
unsigned int lod;
const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
const struct intel_renderbuffer *irb = NULL;
@@ -63,11 +61,11 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
if (!irb)
irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
rb = (struct gl_renderbuffer*) irb;
+ const GLenum gl_target = rb ? brw_get_target(rb) : GL_TEXTURE_2D;
+ const uint32_t surftype = brw_get_surface_type(gl_target);
if (rb) {
depth = MAX2(irb->layer_count, 1);
- if (rb->TexImage)
- gl_target = rb->TexImage->TexObject->Target;
}
switch (gl_target) {
@@ -78,7 +76,6 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
* this. So we use BRW_SURFACE_2D, since for rendering purposes this is
* equivalent.
*/
- surftype = BRW_SURFACE_2D;
depth *= 6;
break;
case GL_TEXTURE_3D:
@@ -86,7 +83,6 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
depth = MAX2(mt->logical_depth0, 1);
/* fallthrough */
default:
- surftype = translate_tex_target(gl_target);
break;
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index b31f491..3c57535 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -452,16 +452,14 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
uint32_t format;
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
- uint32_t surftype;
+ const GLenum gl_target = brw_get_target(rb);
+ const uint32_t surftype = brw_get_surface_type(gl_target);
bool is_array = false;
int depth = MAX2(irb->layer_count, 1);
const uint8_t mocs = GEN7_MOCS_L3;
int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
- GLenum gl_target = rb->TexImage ?
- rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
-
uint32_t surf_index =
brw->wm.prog_data->binding_table.render_target_start + unit;
@@ -484,7 +482,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
case GL_TEXTURE_CUBE_MAP:
- surftype = BRW_SURFACE_2D;
is_array = true;
depth *= 6;
break;
@@ -492,7 +489,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
depth = MAX2(irb->mt->logical_depth0, 1);
/* fallthrough */
default:
- surftype = translate_tex_target(gl_target);
is_array = _mesa_tex_target_is_array(gl_target);
break;
}
--
1.8.3.1
More information about the mesa-dev
mailing list