[Mesa-dev] [PATCH] i965: Put '_default_' in the name of functions that set default state.
Ian Romanick
idr at freedesktop.org
Mon Jun 2 15:28:33 PDT 2014
On 06/01/2014 12:16 AM, Kenneth Graunke wrote:
> Eventually we're going to use functions to set bits on an instruction.
> Putting 'default' in the name of functions that alter default state will
> help distinguins them.
^^^^^^^^^^^ distinguish or pengiuns
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
> This patch was generated entirely mechanically, by the following:
>
> for file in brw*.{cpp,c,h}; do
> sed -i \
> -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \
> -e 's/brw_set_saturate/brw_set_default_saturate/g' \
> -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \
> -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \
> -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \
> -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \
> -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \
> -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \
> $file;
> done
>
> No manual changes were done after running that command.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
> src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 10 +-
> src/mesa/drivers/dri/i965/brw_clip.c | 2 +-
> src/mesa/drivers/dri/i965/brw_clip_tri.c | 6 +-
> src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 4 +-
> src/mesa/drivers/dri/i965/brw_clip_util.c | 14 +--
> src/mesa/drivers/dri/i965/brw_eu.c | 22 ++--
> src/mesa/drivers/dri/i965/brw_eu.h | 16 +--
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 26 ++---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 132 +++++++++++------------
> src/mesa/drivers/dri/i965/brw_gs.c | 2 +-
> src/mesa/drivers/dri/i965/brw_gs_emit.c | 8 +-
> src/mesa/drivers/dri/i965/brw_sf_emit.c | 12 +--
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 72 ++++++-------
> 13 files changed, 163 insertions(+), 163 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> index ea0065a..aeed6c9 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> @@ -440,7 +440,7 @@ brw_blorp_const_color_program::compile(struct brw_context *brw,
>
> alloc_regs();
>
> - brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(&func, BRW_COMPRESSION_NONE);
>
> struct brw_reg mrf_rt_write =
> retype(vec16(brw_message_reg(base_mrf)), BRW_REGISTER_TYPE_F);
> @@ -450,9 +450,9 @@ brw_blorp_const_color_program::compile(struct brw_context *brw,
> /* The message payload is a single register with the low 4 floats/ints
> * filled with the constant clear color.
> */
> - brw_set_mask_control(&func, BRW_MASK_DISABLE);
> + brw_set_default_mask_control(&func, BRW_MASK_DISABLE);
> brw_MOV(&func, vec4(brw_message_reg(base_mrf)), clear_rgba);
> - brw_set_mask_control(&func, BRW_MASK_ENABLE);
> + brw_set_default_mask_control(&func, BRW_MASK_ENABLE);
>
> msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
> mlen = 1;
> @@ -461,11 +461,11 @@ brw_blorp_const_color_program::compile(struct brw_context *brw,
> /* The message payload is pairs of registers for 16 pixels each of r,
> * g, b, and a.
> */
> - brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
> brw_MOV(&func,
> brw_message_reg(base_mrf + i * 2),
> brw_vec1_grf(clear_rgba.nr, i));
> - brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(&func, BRW_COMPRESSION_NONE);
> }
>
> msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
> diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
> index 536c085..12f512d 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip.c
> @@ -86,7 +86,7 @@ static void compile_clip_prog( struct brw_context *brw,
> /* For some reason the thread is spawned with only 4 channels
> * unmasked.
> */
> - brw_set_mask_control(&c.func, BRW_MASK_DISABLE);
> + brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE);
>
>
> /* Would ideally have the option of producing a program which could
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
> index 77cae29..3dd423e 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
> @@ -433,7 +433,7 @@ void brw_clip_tri( struct brw_clip_compile *c )
> BRW_CONDITIONAL_GE,
> c->reg.nr_verts,
> brw_imm_ud(3));
> - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
>
> /* && (planemask>>=1) != 0
> */
> @@ -562,7 +562,7 @@ static void brw_clip_test( struct brw_clip_compile *c )
> brw_clip_kill_thread(c);
> }
> brw_ENDIF(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
>
> /* some vertices are inside a plane, some are outside,need to clip */
> brw_XOR(p, t, t1, t2);
> @@ -600,7 +600,7 @@ static void brw_clip_test( struct brw_clip_compile *c )
> brw_clip_kill_thread(c);
> }
> brw_ENDIF(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
>
> /* some vertices are inside a plane, some are outside,need to clip */
> brw_XOR(p, t, t1, t2);
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
> index 302fdc4..53db8bc 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c
> @@ -85,10 +85,10 @@ static void compute_tri_direction( struct brw_clip_compile *c )
>
> /* Take their crossproduct:
> */
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_MUL(p, vec4(brw_null_reg()), brw_swizzle(e, 1,2,0,3), brw_swizzle(f,2,0,1,3));
> brw_MAC(p, vec4(e), negate(brw_swizzle(e, 2,0,1,3)), brw_swizzle(f,1,2,0,3));
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> brw_MUL(p, c->reg.dir, c->reg.dir, vec4(e));
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
> index 239a04a..5fb46b6 100644
> --- a/src/mesa/drivers/dri/i965/brw_clip_util.c
> +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
> @@ -98,9 +98,9 @@ void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos )
>
> /* value.xyz *= value.rhw
> */
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos, brw_swizzle1(pos, W));
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> }
>
>
> @@ -192,7 +192,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
> /* t_nopersp = vec4(v1.xy, dest.xy) */
> brw_MOV(p, t_nopersp, deref_4f(v1_ptr, delta));
> brw_MOV(p, tmp, deref_4f(dest_ptr, delta));
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_MOV(p,
> brw_writemask(t_nopersp, WRITEMASK_ZW),
> brw_swizzle(tmp, 0, 1, 0, 1));
> @@ -215,7 +215,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
> brw_writemask(t_nopersp, WRITEMASK_XY),
> brw_abs(brw_swizzle(t_nopersp, 0, 2, 0, 0)),
> brw_abs(brw_swizzle(t_nopersp, 1, 3, 0, 0)));
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> /* If the points are in the same place, just substitute a
> * value to avoid divide-by-zero
> @@ -231,9 +231,9 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
> brw_math_invert(p, get_element(t_nopersp, 0), get_element(t_nopersp, 0));
> brw_MUL(p, vec1(t_nopersp), vec1(t_nopersp),
> vec1(suboffset(t_nopersp, 1)));
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_MOV(p, t_nopersp, brw_swizzle(t_nopersp, 0, 0, 0, 0));
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> release_tmp(c, tmp);
> release_tmp(c, v0_ndc_copy);
> @@ -461,7 +461,7 @@ void brw_clip_ff_sync(struct brw_clip_compile *c)
> 0 /* eot */);
> }
> brw_ENDIF(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> }
> }
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
> index 1182182..3ecb4bc 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu.c
> @@ -88,29 +88,29 @@ brw_swap_cmod(uint32_t cmod)
> }
> }
>
> -void brw_set_predicate_control( struct brw_compile *p, unsigned pc )
> +void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc )
> {
> p->current->header.predicate_control = pc;
> }
>
> -void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
> +void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
> {
> p->current->header.predicate_inverse = predicate_inverse;
> }
>
> -void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
> +void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg)
> {
> p->current->bits2.da1.flag_reg_nr = reg;
> p->current->bits2.da1.flag_subreg_nr = subreg;
> }
>
> -void brw_set_access_mode( struct brw_compile *p, unsigned access_mode )
> +void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode )
> {
> p->current->header.access_mode = access_mode;
> }
>
> void
> -brw_set_compression_control(struct brw_compile *p,
> +brw_set_default_compression_control(struct brw_compile *p,
> enum brw_compression compression_control)
> {
> p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
> @@ -146,17 +146,17 @@ brw_set_compression_control(struct brw_compile *p,
> }
> }
>
> -void brw_set_mask_control( struct brw_compile *p, unsigned value )
> +void brw_set_default_mask_control( struct brw_compile *p, unsigned value )
> {
> p->current->header.mask_control = value;
> }
>
> -void brw_set_saturate( struct brw_compile *p, bool enable )
> +void brw_set_default_saturate( struct brw_compile *p, bool enable )
> {
> p->current->header.saturate = enable;
> }
>
> -void brw_set_acc_write_control(struct brw_compile *p, unsigned value)
> +void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
> {
> if (p->brw->gen >= 6)
> p->current->header.acc_wr_control = value;
> @@ -202,9 +202,9 @@ brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
>
> /* Some defaults?
> */
> - brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
> - brw_set_saturate(p, 0);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
> + brw_set_default_saturate(p, 0);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>
> /* Set up control flow stack */
> p->if_stack_depth = 0;
> diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
> index fe57834..c9e5a4b 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu.h
> +++ b/src/mesa/drivers/dri/i965/brw_eu.h
> @@ -98,14 +98,14 @@ struct brw_compile {
>
> void brw_pop_insn_state( struct brw_compile *p );
> void brw_push_insn_state( struct brw_compile *p );
> -void brw_set_mask_control( struct brw_compile *p, unsigned value );
> -void brw_set_saturate( struct brw_compile *p, bool enable );
> -void brw_set_access_mode( struct brw_compile *p, unsigned access_mode );
> -void brw_set_compression_control(struct brw_compile *p, enum brw_compression c);
> -void brw_set_predicate_control( struct brw_compile *p, unsigned pc );
> -void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse);
> -void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg);
> -void brw_set_acc_write_control(struct brw_compile *p, unsigned value);
> +void brw_set_default_mask_control( struct brw_compile *p, unsigned value );
> +void brw_set_default_saturate( struct brw_compile *p, bool enable );
> +void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode );
> +void brw_set_default_compression_control(struct brw_compile *p, enum brw_compression c);
> +void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc );
> +void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse);
> +void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg);
> +void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value);
>
> void brw_init_compile(struct brw_context *, struct brw_compile *p,
> void *mem_ctx);
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index a6d5941..b89070b 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -72,8 +72,8 @@ gen6_resolve_implied_move(struct brw_compile *p,
>
> if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) {
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
> retype(*src, BRW_REGISTER_TYPE_UD));
> brw_pop_insn_state(p);
> @@ -1982,8 +1982,8 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
> */
> {
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>
> brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
>
> @@ -2090,8 +2090,8 @@ brw_oword_block_read_scratch(struct brw_compile *p,
>
> {
> brw_push_insn_state(p);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>
> brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
>
> @@ -2193,9 +2193,9 @@ void brw_oword_block_read(struct brw_compile *p,
> mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
>
> brw_push_insn_state(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>
> brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
>
> @@ -2368,8 +2368,8 @@ void brw_urb_WRITE(struct brw_compile *p,
> if (brw->gen == 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
> /* Enable Channel Masks in the URB_WRITE_HWORD message header */
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5),
> BRW_REGISTER_TYPE_UD),
> retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
> @@ -2735,8 +2735,8 @@ void brw_shader_time_add(struct brw_compile *p,
> assert(brw->gen >= 7);
>
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
> brw_pop_insn_state(p);
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index cc6ae00..bbbe687 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -106,9 +106,9 @@ fs_generator::generate_fb_write(fs_inst *inst)
> * move, here's g1.
> */
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>
> if (inst->header_present) {
> /* On HSW, the GPU will use the predicate on SENDC, unless the header is
> @@ -126,11 +126,11 @@ fs_generator::generate_fb_write(fs_inst *inst)
> }
>
> if (brw->gen >= 6) {
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> brw_MOV(p,
> retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
> retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>
> if (inst->target > 0 && key->replicate_alpha) {
> /* Set "Source0 Alpha Present to RenderTarget" bit in message
> @@ -231,7 +231,7 @@ fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
> * don't do compression in the SIMD16 case.
> */
> brw_push_insn_state(p);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_ADD(p, dst, src, deltas);
> brw_pop_insn_state(p);
> }
> @@ -286,7 +286,7 @@ fs_generator::generate_math1_gen6(fs_inst *inst,
>
> assert(inst->mlen == 0);
>
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_math(p, dst,
> op,
> 0, src0,
> @@ -294,13 +294,13 @@ fs_generator::generate_math1_gen6(fs_inst *inst,
> BRW_MATH_PRECISION_FULL);
>
> if (dispatch_width == 16) {
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_math(p, sechalf(dst),
> op,
> 0, sechalf(src0),
> BRW_MATH_DATA_VECTOR,
> BRW_MATH_PRECISION_FULL);
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> }
> }
>
> @@ -314,13 +314,13 @@ fs_generator::generate_math2_gen6(fs_inst *inst,
>
> assert(inst->mlen == 0);
>
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_math2(p, dst, op, src0, src1);
>
> if (dispatch_width == 16) {
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> }
> }
>
> @@ -333,7 +333,7 @@ fs_generator::generate_math_gen4(fs_inst *inst,
>
> assert(inst->mlen >= 1);
>
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_math(p, dst,
> op,
> inst->base_mrf, src,
> @@ -341,14 +341,14 @@ fs_generator::generate_math_gen4(fs_inst *inst,
> BRW_MATH_PRECISION_FULL);
>
> if (dispatch_width == 16) {
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_math(p, sechalf(dst),
> op,
> inst->base_mrf + 1, sechalf(src),
> BRW_MATH_DATA_VECTOR,
> BRW_MATH_PRECISION_FULL);
>
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> }
> }
>
> @@ -565,8 +565,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
> }
>
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> /* Explicitly set up the message header by copying g0 to the MRF. */
> brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
>
> @@ -724,15 +724,15 @@ fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src
> BRW_HORIZONTAL_STRIDE_1,
> BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> if (unroll_to_simd8)
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> if (negate_value)
> brw_ADD(p, dst, src1, negate(src0));
> else
> brw_ADD(p, dst, src0, negate(src1));
> if (unroll_to_simd8) {
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> src0 = sechalf(src0);
> src1 = sechalf(src1);
> dst = sechalf(dst);
> @@ -775,7 +775,7 @@ fs_generator::generate_discard_jump(fs_inst *inst)
> this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
>
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> gen6_HALT(p);
> brw_pop_insn_state(p);
> }
> @@ -846,8 +846,8 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
> offset = brw_vec1_grf(offset.nr, 0);
>
> brw_push_insn_state(p);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
> brw_pop_insn_state(p);
>
> @@ -1000,7 +1000,7 @@ fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
> dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
>
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_MOV(p, flags, dispatch_mask);
> brw_pop_insn_state(p);
> }
> @@ -1096,8 +1096,8 @@ fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
> assert(value.file == BRW_IMMEDIATE_VALUE);
>
> brw_push_insn_state(p);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
> brw_pop_insn_state(p);
> }
> @@ -1127,8 +1127,8 @@ fs_generator::generate_set_omask(fs_inst *inst,
> if (dispatch_width == 16)
> dst = vec16(dst);
> brw_push_insn_state(p);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>
> if (stride_8_8_1) {
> brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
> @@ -1153,8 +1153,8 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
> src0.type == BRW_REGISTER_TYPE_UD);
>
> brw_push_insn_state(p);
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
> brw_ADD(p, dst, src0, reg);
> if (dispatch_width == 16)
> @@ -1259,7 +1259,7 @@ fs_generator::generate_shader_time_add(fs_inst *inst,
> {
> assert(brw->gen >= 7);
> brw_push_insn_state(p);
> - brw_set_mask_control(p, true);
> + brw_set_default_mask_control(p, true);
>
> assert(payload.file == BRW_GENERAL_REGISTER_FILE);
> struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
> @@ -1368,19 +1368,19 @@ fs_generator::generate_code(exec_list *instructions,
> }
> dst = brw_reg_from_fs_reg(&inst->dst);
>
> - brw_set_predicate_control(p, inst->predicate);
> - brw_set_predicate_inverse(p, inst->predicate_inverse);
> - brw_set_flag_reg(p, 0, inst->flag_subreg);
> - brw_set_saturate(p, inst->saturate);
> - brw_set_mask_control(p, inst->force_writemask_all);
> - brw_set_acc_write_control(p, inst->writes_accumulator);
> + brw_set_default_predicate_control(p, inst->predicate);
> + brw_set_default_predicate_inverse(p, inst->predicate_inverse);
> + brw_set_default_flag_reg(p, 0, inst->flag_subreg);
> + brw_set_default_saturate(p, inst->saturate);
> + brw_set_default_mask_control(p, inst->force_writemask_all);
> + brw_set_default_acc_write_control(p, inst->writes_accumulator);
>
> if (inst->force_uncompressed || dispatch_width == 8) {
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> } else if (inst->force_sechalf) {
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> } else {
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> }
>
> switch (inst->opcode) {
> @@ -1402,32 +1402,32 @@ fs_generator::generate_code(exec_list *instructions,
>
> case BRW_OPCODE_MAD:
> assert(brw->gen >= 6);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> if (dispatch_width == 16 && !brw->is_haswell) {
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_MAD(p, dst, src[0], src[1], src[2]);
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> } else {
> brw_MAD(p, dst, src[0], src[1], src[2]);
> }
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> break;
>
> case BRW_OPCODE_LRP:
> assert(brw->gen >= 6);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> if (dispatch_width == 16 && !brw->is_haswell) {
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_LRP(p, dst, src[0], src[1], src[2]);
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> } else {
> brw_LRP(p, dst, src[0], src[1], src[2]);
> }
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> break;
>
> case BRW_OPCODE_FRC:
> @@ -1513,17 +1513,17 @@ fs_generator::generate_code(exec_list *instructions,
>
> case BRW_OPCODE_BFE:
> assert(brw->gen >= 7);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> if (dispatch_width == 16 && !brw->is_haswell) {
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_BFE(p, dst, src[0], src[1], src[2]);
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> } else {
> brw_BFE(p, dst, src[0], src[1], src[2]);
> }
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> break;
>
> case BRW_OPCODE_BFI1:
> @@ -1534,18 +1534,18 @@ fs_generator::generate_code(exec_list *instructions,
> * "Force BFI instructions to be executed always in SIMD8."
> */
> if (dispatch_width == 16 && brw->is_haswell) {
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_BFI1(p, dst, src[0], src[1]);
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> } else {
> brw_BFI1(p, dst, src[0], src[1]);
> }
> break;
> case BRW_OPCODE_BFI2:
> assert(brw->gen >= 7);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
> * should
> *
> @@ -1555,15 +1555,15 @@ fs_generator::generate_code(exec_list *instructions,
> * do for the other three-source instructions.
> */
> if (dispatch_width == 16) {
> - brw_set_compression_control(p, BRW_COMPRESSION_NONE);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> brw_BFI2(p, dst, src[0], src[1], src[2]);
> - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
> brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> } else {
> brw_BFI2(p, dst, src[0], src[1], src[2]);
> }
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> break;
>
> case BRW_OPCODE_IF:
> @@ -1589,7 +1589,7 @@ fs_generator::generate_code(exec_list *instructions,
>
> case BRW_OPCODE_BREAK:
> brw_BREAK(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> break;
> case BRW_OPCODE_CONTINUE:
> /* FINISHME: We need to write the loop instruction support still. */
> @@ -1597,7 +1597,7 @@ fs_generator::generate_code(exec_list *instructions,
> gen6_CONT(p);
> else
> brw_CONT(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> break;
>
> case BRW_OPCODE_WHILE:
> @@ -1815,7 +1815,7 @@ fs_generator::generate_assembly(exec_list *simd8_instructions,
> /* Save off the start of this SIMD16 program */
> prog_data->prog_offset_16 = p->next_insn_offset;
>
> - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
> + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
>
> struct annotation_info annotation;
> memset(&annotation, 0, sizeof(annotation));
> diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
> index 97a2ee3..9683fc6 100644
> --- a/src/mesa/drivers/dri/i965/brw_gs.c
> +++ b/src/mesa/drivers/dri/i965/brw_gs.c
> @@ -70,7 +70,7 @@ static void compile_ff_gs_prog(struct brw_context *brw,
> /* For some reason the thread is spawned with only 4 channels
> * unmasked.
> */
> - brw_set_mask_control(&c.func, BRW_MASK_DISABLE);
> + brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE);
>
> if (brw->gen >= 6) {
> unsigned num_verts;
> diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c
> index 58b9d86..cb9dd7b 100644
> --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
> @@ -444,10 +444,10 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
> /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
> vertex_slot.dw1.bits.swizzle = varying == VARYING_SLOT_PSIZ
> ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_MOV(p, stride(c->reg.header, 4, 4, 1),
> retype(vertex_slot, BRW_REGISTER_TYPE_UD));
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> brw_svb_write(p,
> final_write ? c->reg.temp : brw_null_reg(), /* dest */
> 1, /* msg_reg_nr */
> @@ -518,10 +518,10 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
> get_element_ud(c->reg.R0, 2),
> brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
> brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
> - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
> }
> brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> brw_ff_gs_emit_vue(c, c->reg.vertex[2], true);
> break;
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c
> index 8897596..b526a5c 100644
> --- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
> @@ -500,7 +500,7 @@ void brw_emit_tri_setup(struct brw_sf_compile *c, bool allocate)
> }
> }
>
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> }
>
>
> @@ -574,7 +574,7 @@ void brw_emit_line_setup(struct brw_sf_compile *c, bool allocate)
> }
> }
>
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> }
>
> void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
> @@ -619,7 +619,7 @@ void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
> BRW_MATH_DATA_SCALAR,
> BRW_MATH_PRECISION_FULL);
>
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
>
> /* dA/dx, dA/dy */
> brw_MOV(p, c->m1Cx, brw_imm_f(0.0));
> @@ -639,7 +639,7 @@ void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
> brw_MOV(p, brw_writemask(c->m3C0, WRITEMASK_W), brw_imm_f(1.0));
> }
>
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> }
>
> if (pc & ~pc_coord_replace) {
> @@ -664,7 +664,7 @@ void brw_emit_point_sprite_setup(struct brw_sf_compile *c, bool allocate)
> BRW_URB_SWIZZLE_TRANSPOSE);
> }
>
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> }
>
> /* Points setup - several simplifications as all attributes are
> @@ -726,7 +726,7 @@ void brw_emit_point_setup(struct brw_sf_compile *c, bool allocate)
> }
> }
>
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> }
>
> static void
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index 3844407..0791df6 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -185,7 +185,7 @@ vec4_generator::generate_math1_gen6(vec4_instruction *inst,
> assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
> check_gen6_math_src_arg(src);
>
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> brw_math(p,
> dst,
> brw_math_function(inst->opcode),
> @@ -193,7 +193,7 @@ vec4_generator::generate_math1_gen6(vec4_instruction *inst,
> src,
> BRW_MATH_DATA_SCALAR,
> BRW_MATH_PRECISION_FULL);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> }
>
> void
> @@ -220,12 +220,12 @@ vec4_generator::generate_math2_gen6(vec4_instruction *inst,
> check_gen6_math_src_arg(src0);
> check_gen6_math_src_arg(src1);
>
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> brw_math2(p,
> dst,
> brw_math_function(inst->opcode),
> src0, src1);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> }
>
> void
> @@ -248,8 +248,8 @@ vec4_generator::generate_math2_gen4(vec4_instruction *inst,
> struct brw_reg &op1 = is_int_div ? src0 : src1;
>
> brw_push_insn_state(p);
> - brw_set_saturate(p, false);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_saturate(p, false);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
> brw_pop_insn_state(p);
>
> @@ -369,10 +369,10 @@ vec4_generator::generate_tex(vec4_instruction *inst,
>
> /* Explicitly set up the message header by copying g0 to the MRF. */
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
>
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> if (inst->texture_offset) {
> /* Set the texel offset bits in DWord 2. */
> @@ -503,11 +503,11 @@ vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
> * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
> */
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
> src1);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_pop_insn_state(p);
> }
>
> @@ -516,8 +516,8 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
> struct brw_reg src)
> {
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>
> /* If we think of the src and dst registers as composed of 8 DWORDs each,
> * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
> @@ -534,7 +534,7 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
> */
> brw_MOV(p, suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
> stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_pop_insn_state(p);
> }
>
> @@ -545,10 +545,10 @@ vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
> assert(src.file == BRW_IMMEDIATE_VALUE);
>
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_MOV(p, suboffset(vec1(dst), 2), src);
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> brw_pop_insn_state(p);
> }
>
> @@ -563,8 +563,8 @@ vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
> */
> dst = suboffset(vec1(dst), 4);
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_SHL(p, dst, dst, brw_imm_ud(4));
> brw_pop_insn_state(p);
> }
> @@ -626,8 +626,8 @@ vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
> dst = retype(dst, BRW_REGISTER_TYPE_UB);
> src = retype(src, BRW_REGISTER_TYPE_UB);
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
> brw_pop_insn_state(p);
> }
> @@ -641,7 +641,7 @@ vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
> * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
> */
> brw_push_insn_state(p);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> dst = retype(dst, BRW_REGISTER_TYPE_UD);
> struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
> brw_SHR(p, dst, stride(r0, 1, 4, 0),
> @@ -671,8 +671,8 @@ vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
> struct brw_reg index_4 = suboffset(vec1(index), 4);
>
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> brw_MOV(p, m1_0, index_0);
>
> @@ -691,8 +691,8 @@ vec4_generator::generate_unpack_flags(vec4_instruction *inst,
> struct brw_reg dst)
> {
> brw_push_insn_state(p);
> - brw_set_mask_control(p, BRW_MASK_DISABLE);
> - brw_set_access_mode(p, BRW_ALIGN_1);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> struct brw_reg flags = brw_flag_reg(0, 0);
> struct brw_reg dst_0 = suboffset(vec1(dst), 0);
> @@ -756,7 +756,7 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst,
> /* If the instruction is predicated, we'll predicate the send, not
> * the header setup.
> */
> - brw_set_predicate_control(p, false);
> + brw_set_default_predicate_control(p, false);
>
> gen6_resolve_implied_move(p, &header, inst->base_mrf);
>
> @@ -776,7 +776,7 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst,
> else
> msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
>
> - brw_set_predicate_control(p, inst->predicate);
> + brw_set_default_predicate_control(p, inst->predicate);
>
> /* Pre-gen6, we have to specify write commits to ensure ordering
> * between reads and writes within a thread. Afterwards, that's
> @@ -1124,7 +1124,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
>
> case BRW_OPCODE_BREAK:
> brw_BREAK(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> break;
> case BRW_OPCODE_CONTINUE:
> /* FINISHME: We need to write the loop instruction support still. */
> @@ -1132,7 +1132,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
> gen6_CONT(p);
> else
> brw_CONT(p);
> - brw_set_predicate_control(p, BRW_PREDICATE_NONE);
> + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
> break;
>
> case BRW_OPCODE_WHILE:
> @@ -1290,11 +1290,11 @@ vec4_generator::generate_code(exec_list *instructions,
> }
> dst = inst->get_dst();
>
> - brw_set_predicate_control(p, inst->predicate);
> - brw_set_predicate_inverse(p, inst->predicate_inverse);
> - brw_set_saturate(p, inst->saturate);
> - brw_set_mask_control(p, inst->force_writemask_all);
> - brw_set_acc_write_control(p, inst->writes_accumulator);
> + brw_set_default_predicate_control(p, inst->predicate);
> + brw_set_default_predicate_inverse(p, inst->predicate_inverse);
> + brw_set_default_saturate(p, inst->saturate);
> + brw_set_default_mask_control(p, inst->force_writemask_all);
> + brw_set_default_acc_write_control(p, inst->writes_accumulator);
>
> unsigned pre_emit_nr_insn = p->nr_insn;
>
> @@ -1327,7 +1327,7 @@ vec4_generator::generate_assembly(exec_list *instructions,
> struct annotation_info annotation;
> memset(&annotation, 0, sizeof(annotation));
>
> - brw_set_access_mode(p, BRW_ALIGN_16);
> + brw_set_default_access_mode(p, BRW_ALIGN_16);
> generate_code(instructions, &annotation);
> brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
>
>
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