[Mesa-dev] i965/fs: Stencil texturing on gen6/7

Topi Pohjolainen topi.pohjolainen at intel.com
Mon Jun 9 00:45:34 PDT 2014

This series augments the compiler backend for fragment shaders to support
sampling of W-tiled stencil buffers. This capability can be already found
in the blorp programs making copies of stencil buffers.
Just as in case of blorp the buffers are configured as Y-tiled and the
programs are augmented with instructions that translate coordinates
between the two (W and Y) tiling spaces.
Here in addition one does not sample one pixel at a time but a 2x2 block
instead. This removes the current restriction imposed on textures sizes as
the blit does not anymore require width larger than the original to be
configured for the sampling engine.

On ivb and hsw the coordinate translations support dynamic offseting to
layers and mip-levels. Surfaces are configured for the sampling engine
as having single levels covering the entire slice. The program offsets
coordinates to desired mip-level with the slice. On snb this doesn't
unfortunately work as snb does not have a switch telling the hardware
that there is no miptree but single level only. For internal stencil
blits snb is fixed to desired layer and mip-level using the tile x/y
I have additional stencil texturing piglit tests exercising combined
layer and mip-level access which I'll try to submit for review asap
On ivb and hsw only feature missing for fragment program stencil
texturing is clamping. For vertex shaders there is still need to
construct similar compiler backend support as for fragment programs.

Dynamic mip-level offseting requires the program to know the base
level dimensions for the texture. As the surface is configured for
full slice dimensions it is not possible to simply query these from the
hardware. (Base level dimensions could be reverse calculated from the
slice dimensions except they would be aligned - correct offseting needs
the original unaligned).
For this purpose fragment programs are augmented with two new builtin
uniforms - base width and base height. Unlike the rectangle scale these
are also supported for 16-width.

Sampling engine is always fed with texel coordinates and even on snb
(that would natively support texturing of interleaved msaa) surfaces
are always configured as single sampled and the program encodes
individual sample positions into the coordinates.

The series finally enables meta stencil blits meaning that blorp stencil
support isn't needed anymore (on any hardware). The signaling for the
stencil mode is now done internally via brw_context as the texture
parameter approach would only work when the stencil extension is itself
is fully enabled.

This sits on top of my fs/vec4 restructure series and additionally
requires Jordan's patches removing the need for temporary software
copies of small stencil buffers. Without there are random artifacts that
seem to originate from the copy not being fully written out before the
blit. Kenneth and I've been looking into this a little but the root
cause is yet to be understood.

This can be found in:

git://people.freedesktop.org/~tpohjola/mesa stencil_meta_blit_gen6

Topi Pohjolainen (22):
  i965/meta: Add means for signaling meta blit surface overrides
  i965/gen8: Follow stencil meta blit overrides in the context
  i965/gen8: Take into account stencil meta blit layer override
  i965/fs: Add generator support for fetching texture dimensions
  i965/fs: Recompile when switching to/from stencil indexing
  i965/fs/gen6: Use stencil indexing if stencil meta blit is active
  i965/gen6: Surface state overrides for sampling w-tiled as y-tiled
  i965: Add helper for determining if miptree represents stencil buffer
  i965/gen7: Use helper variables for texture surface parameters
  i965/gen6: Use helper variables for texture surface parameters
  i965/gen7: Configure msaa stencil buffers as single sampled
  i965/gen6: Configure msaa stencil buffers as single sampled
  i965/gen7: Configure w-tiled surfaces as y-tiled
  i965/gen6: Configure w-tiled surfaces as y-tiled
  i965/gen6: Add tile offset support for texture surfaces
  i965/gen6: Offset stencil texture surfaces directly to level/layer
  i965: Keep track of texture base dimensions
  i965/fs/gen6: Support for sampling stencil with non-msaa coordinates
  i965/fs/gen6: Support for sampling stencil with msaa coordinates
  i965/fs/gen6: Support for sampling stencil with noormalized
  i965/fb/gen6: Use meta path for stencil blits
  i965/fb/gen6: Use meta path for stencil up/downsampling

 src/mesa/drivers/dri/i965/Makefile.sources        |   1 +
 src/mesa/drivers/dri/i965/brw_context.c           |  10 +
 src/mesa/drivers/dri/i965/brw_context.h           |  27 ++
 src/mesa/drivers/dri/i965/brw_defines.h           |   2 +
 src/mesa/drivers/dri/i965/brw_fs.cpp              |   1 +
 src/mesa/drivers/dri/i965/brw_fs.h                |   6 +-
 src/mesa/drivers/dri/i965/brw_fs_fp.cpp           |   3 +-
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp    |  33 ++
 src/mesa/drivers/dri/i965/brw_fs_stencil_tex.cpp  | 549 ++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_fs_stencil_tex.h    |  75 +++
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp      |  34 +-
 src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c |  14 +-
 src/mesa/drivers/dri/i965/brw_program.h           |  20 +
 src/mesa/drivers/dri/i965/brw_shader.cpp          |   2 +
 src/mesa/drivers/dri/i965/brw_state.h             |  10 +
 src/mesa/drivers/dri/i965/brw_wm.c                |  18 +
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c  | 122 ++++-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |  95 ++--
 src/mesa/drivers/dri/i965/gen8_surface_state.c    |   6 +-
 src/mesa/drivers/dri/i965/intel_fbo.c             |  16 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c     |  31 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h     |   6 +
 src/mesa/drivers/dri/i965/intel_tex.c             |  49 ++
 23 files changed, 1033 insertions(+), 97 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/brw_fs_stencil_tex.cpp
 create mode 100644 src/mesa/drivers/dri/i965/brw_fs_stencil_tex.h


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