[Mesa-dev] [PATCH 09/22] i965/gen7: Use helper variables for texture surface parameters

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 34 ++++++++++++++---------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index b31f491..f12f215 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -283,6 +283,13 @@ gen7_update_texture_surface(struct gl_context *ctx,
       return;
    }
 
+   unsigned width = mt->logical_width0;
+   unsigned height = mt->logical_height0;
+   unsigned pitch = mt->pitch;
+   uint32_t tiling = mt->tiling;
+   unsigned min_lod = tObj->MinLevel + tObj->BaseLevel - mt->first_level;
+   unsigned mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
+
    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
                                     8 * 4, 32, surf_offset);
    memset(surf, 0, 8 * 4);
@@ -296,7 +303,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
 
    surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
              tex_format << BRW_SURFACE_FORMAT_SHIFT |
-             gen7_surface_tiling_mode(mt->tiling);
+             gen7_surface_tiling_mode(tiling);
 
    /* mask of faces present in cube map; for other surfaces MBZ. */
    if (tObj->Target == GL_TEXTURE_CUBE_MAP || tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
@@ -321,11 +328,10 @@ gen7_update_texture_surface(struct gl_context *ctx,
 
    surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
 
-   surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
-             SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
+   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 
-   surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) |
-             (mt->pitch - 1);
+   surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
 
    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
              SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
@@ -333,9 +339,8 @@ gen7_update_texture_surface(struct gl_context *ctx,
                        GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
 
    surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
-              SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level, GEN7_SURFACE_MIN_LOD) |
-              /* mip count */
-              (intelObj->_MaxLevel - tObj->BaseLevel));
+              SET_FIELD(min_lod, GEN7_SURFACE_MIN_LOD) |
+              mip_count);
 
    if (brw->is_haswell) {
       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
@@ -449,6 +454,10 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_mipmap_tree *mt = irb->mt;
+   unsigned width = mt->logical_width0;
+   unsigned height = mt->logical_height0;
+   unsigned pitch = mt->pitch;
+   uint32_t tiling = mt->tiling;
    uint32_t format;
    /* _NEW_BUFFERS */
    mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
@@ -501,7 +510,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
              format << BRW_SURFACE_FORMAT_SHIFT |
              (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
                                           : GEN7_SURFACE_ARYSPC_FULL) |
-             gen7_surface_tiling_mode(mt->tiling);
+             gen7_surface_tiling_mode(tiling);
 
    if (irb->mt->align_h == 4)
       surf[0] |= GEN7_SURFACE_VALIGN_4;
@@ -519,11 +528,10 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
              (irb->mt_level - irb->mt->first_level);
 
-   surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
-             SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
+   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 
-   surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) |
-             (mt->pitch - 1);
+   surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) | (pitch - 1);
 
    surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) |
              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
-- 
1.8.3.1