[Mesa-dev] [PATCH 04/22] i965/fs: Add generator support for fetching texture dimensions

[Pohjolainen, Topi]

On Mon, Jun 09, 2014 at 07:56:46PM +1200, Chris Forbes wrote:
> How is this different from the existing SHADER_OPCODE_TXS?

Hold on, I'll need to go and check. There was a definite reason, I
remember the original having a restriction of some kind.

But anyway, this is an oversight of mine - this is not needed by the
series anymore. Thanks for asking!

> 
> On Mon, Jun 9, 2014 at 7:45 PM, Topi Pohjolainen
> <topi.pohjolainen at intel.com> wrote:
> > Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> > ---
> >  src/mesa/drivers/dri/i965/brw_defines.h        |  2 ++
> >  src/mesa/drivers/dri/i965/brw_fs.cpp           |  1 +
> >  src/mesa/drivers/dri/i965/brw_fs.h             |  3 +++
> >  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 33 ++++++++++++++++++++++++++
> >  src/mesa/drivers/dri/i965/brw_shader.cpp       |  2 ++
> >  5 files changed, 41 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 3afd399..7ffa520 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -798,6 +798,8 @@ enum opcode {
> >     SHADER_OPCODE_TG4,
> >     SHADER_OPCODE_TG4_OFFSET,
> >
> > +   SHADER_OPCODE_TEX_RESINFO,
> > +
> >     SHADER_OPCODE_SHADER_TIME_ADD,
> >
> >     SHADER_OPCODE_UNTYPED_ATOMIC,
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> > index 246aa15..ff81779 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> > @@ -625,6 +625,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
> >     case SHADER_OPCODE_TXF_MCS:
> >     case SHADER_OPCODE_TG4:
> >     case SHADER_OPCODE_TG4_OFFSET:
> > +   case SHADER_OPCODE_TEX_RESINFO:
> >     case SHADER_OPCODE_TXL:
> >     case SHADER_OPCODE_TXS:
> >     case SHADER_OPCODE_LOD:
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
> > index c0d4bd2..55877c1 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs.h
> > +++ b/src/mesa/drivers/dri/i965/brw_fs.h
> > @@ -371,6 +371,9 @@ private:
> >     void generate_linterp(fs_inst *inst, struct brw_reg dst,
> >                          struct brw_reg *src);
> >     void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
> > +   void generate_tex_resinfo(fs_inst *inst,
> > +                             struct brw_reg dst,
> > +                             struct brw_reg src);
> >     void generate_math1_gen7(fs_inst *inst,
> >                             struct brw_reg dst,
> >                             struct brw_reg src);
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> > index 3ff7682..b15aa9f 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> > @@ -617,6 +617,36 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
> >     brw_mark_surface_used(&prog_data->base, surface_index);
> >  }
> >
> > +void
> > +fs_generator::generate_tex_resinfo(fs_inst *inst,
> > +                                   struct brw_reg dst,
> > +                                   struct brw_reg src)
> > +{
> > +   const uint32_t surface_index =
> > +      prog_data->base.binding_table.texture_start + inst->sampler;
> > +   const uint32_t simd_mode = (dispatch_width == 16 &&
> > +                               !inst->force_uncompressed &&
> > +                               !inst->force_sechalf) ?
> > +                                  BRW_SAMPLER_SIMD_MODE_SIMD16 :
> > +                                  BRW_SAMPLER_SIMD_MODE_SIMD8;
> > +
> > +   assert(brw->gen >= 5);
> > +
> > +   brw_SAMPLE(p,
> > +              retype(dst, BRW_REGISTER_TYPE_UW),
> > +              brw->gen >= 7 ? -1 : 2,
> > +              src,
> > +              surface_index,
> > +              inst->sampler % 16,
> > +              GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
> > +              simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD8 ? 4 : 8,
> > +              simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD8 ? 1 : 2,
> > +              false,
> > +              simd_mode,
> > +              BRW_SAMPLER_RETURN_FORMAT_UINT32);
> > +
> > +   brw_mark_surface_used(&prog_data->base, surface_index);
> > +}
> >
> >  /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
> >   * looking like:
> > @@ -1646,6 +1676,9 @@ fs_generator::generate_code(exec_list *instructions)
> >        case SHADER_OPCODE_TG4_OFFSET:
> >          generate_tex(inst, dst, src[0]);
> >          break;
> > +      case SHADER_OPCODE_TEX_RESINFO:
> > +        generate_tex_resinfo(inst, dst, src[0]);
> > +        break;
> >        case FS_OPCODE_DDX:
> >          generate_ddx(inst, dst, src[0]);
> >          break;
> > diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
> > index b94f9de..b831ef4 100644
> > --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> > @@ -451,6 +451,8 @@ brw_instruction_name(enum opcode op)
> >        return "tg4";
> >     case SHADER_OPCODE_TG4_OFFSET:
> >        return "tg4_offset";
> > +   case SHADER_OPCODE_TEX_RESINFO:
> > +      return "tex_resinfo";
> >
> >     case SHADER_OPCODE_GEN4_SCRATCH_READ:
> >        return "gen4_scratch_read";
> > --
> > 1.8.3.1
> >
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