[Mesa-dev] [PATCH] i965/gen8: Align hiz depth clear to 8x4

[Kenneth Graunke]

On Friday, June 13, 2014 03:11:00 PM Kenneth Graunke wrote:
> On Friday, June 13, 2014 12:38:43 PM Topi Pohjolainen wrote:
> > This fixes framebuffer_blit_functionality_scissor_blit.test in
> > gles3 cts.
> > 
> > Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> > ---
> >  src/mesa/drivers/dri/i965/gen8_depth_state.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > index 8c70c62..7f1c23d 100644
> > --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > @@ -30,6 +30,17 @@
> >  #include "brw_defines.h"
> >  
> >  /**
> > + * The documentation for Broadwell's Hierarchical Depth Buffer Resolve 
and 
> for
> > + * Depth Buffer Clear mandates the rectangle to be 8x4 aligned.
> > + */
> > +static void
> > +align_rectangle_primitive(uint32_t *width, uint32_t *height)
> > +{
> > +   *width = ALIGN(*width, 8);
> > +   *height = ALIGN(*height, 4);
> > +}
> > +
> > +/**
> >   * Helper function to emit depth related command packets.
> >   */
> >  static void
> > @@ -54,6 +65,8 @@ emit_depth_packets(struct brw_context *brw,
> >        return;
> >     }
> >  
> > +   align_rectangle_primitive(&width, &height);
> > +
> >     intel_emit_depth_stall_flushes(brw);
> >  
> >     /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
> > @@ -248,6 +261,8 @@ gen8_hiz_exec(struct brw_context *brw, struct 
> intel_mipmap_tree *mt,
> >     unsigned rect_width = minify(mt->logical_width0, level);
> >     unsigned rect_height = minify(mt->logical_height0, level);
> >  
> > +   align_rectangle_primitive(&rect_width, &rect_height);
> > +
> >     BEGIN_BATCH(4);
> >     OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
> >     OUT_BATCH(0);
> > 
> 
> NAK - unfortunately, this regresses piles and piles of depthstencil-render-
> miplevels Piglit tests.  I'll look into why - I'm still convinced we need to 
> do this, we're just probably not doing it quite right.
> 
> --Ken

Oh, amusingly, the align_rectangle_primitive call in emit_depth_packets broke 
the non-HiZ case.  Not all miplevels are 8x4 aligned.  For example, the 
miplevels of a 146x146 texture are layed out like this:

intel_miptree_set_level_info level 0, depth 1, offset 0,0
intel_miptree_set_level_info level 1, depth 1, offset 0,148
intel_miptree_set_level_info level 2, depth 1, offset 76,148
intel_miptree_set_level_info level 3, depth 1, offset 76,184
intel_miptree_set_level_info level 4, depth 1, offset 76,204
intel_miptree_set_level_info level 5, depth 1, offset 76,216
intel_miptree_set_level_info level 6, depth 1, offset 76,220
intel_miptree_set_level_info level 7, depth 1, offset 76,224

HiZ will only be enabled for slice 0.

Miplevel 1 is below the base level, with width 146/2 = 73.  With your patch, 
we configured it for rendering as ALIGN(73, 8) = 80 wide.  So, rendering to 
miplevel 1 would clobber leftmost 4 pixels of data in miplevels >= 2.

I'll send out a fixed patch shortly - running tests now.

--Ken
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