[Mesa-dev] [PATCH 03/19] i965: Convert brw_eu.[ch] to use the new brw_inst API.

[Matt Turner]

From: Kenneth Graunke <kenneth at whitecape.org>

Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_eu.c | 30 +++++++++++++++---------------
 src/mesa/drivers/dri/i965/brw_eu.h |  3 ++-
 2 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index d2ff3f5..08fbf0b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -90,23 +90,23 @@ brw_swap_cmod(uint32_t cmod)
 
 void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc )
 {
-   p->current->header.predicate_control = pc;
+   brw_inst_set_pred_control(p->brw, p->current, pc);
 }
 
 void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
 {
-   p->current->header.predicate_inverse = predicate_inverse;
+   brw_inst_set_pred_inv(p->brw, p->current, predicate_inverse);
 }
 
 void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg)
 {
-   p->current->bits2.da1.flag_reg_nr = reg;
-   p->current->bits2.da1.flag_subreg_nr = subreg;
+   brw_inst_set_flag_reg_nr(p->brw, p->current, reg);
+   brw_inst_set_flag_subreg_nr(p->brw, p->current, subreg);
 }
 
 void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode )
 {
-   p->current->header.access_mode = access_mode;
+   brw_inst_set_access_mode(p->brw, p->current, access_mode);
 }
 
 void
@@ -126,36 +126,36 @@ brw_set_default_compression_control(struct brw_compile *p,
 	 /* This is the "use the first set of bits of dmask/vmask/arf
 	  * according to execsize" option.
 	  */
-	 p->current->header.compression_control = GEN6_COMPRESSION_1Q;
+         brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1Q);
 	 break;
       case BRW_COMPRESSION_2NDHALF:
 	 /* For SIMD8, this is "use the second set of 8 bits." */
-	 p->current->header.compression_control = GEN6_COMPRESSION_2Q;
+         brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_2Q);
 	 break;
       case BRW_COMPRESSION_COMPRESSED:
 	 /* For SIMD16 instruction compression, use the first set of 16 bits
 	  * since we don't do SIMD32 dispatch.
 	  */
-	 p->current->header.compression_control = GEN6_COMPRESSION_1H;
+         brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
 	 break;
       default:
 	 assert(!"not reached");
-	 p->current->header.compression_control = GEN6_COMPRESSION_1H;
+         brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
 	 break;
       }
    } else {
-      p->current->header.compression_control = compression_control;
+      brw_inst_set_qtr_control(brw, p->current, compression_control);
    }
 }
 
 void brw_set_default_mask_control( struct brw_compile *p, unsigned value )
 {
-   p->current->header.mask_control = value;
+   brw_inst_set_mask_control(p->brw, p->current, value);
 }
 
 void brw_set_default_saturate( struct brw_compile *p, bool enable )
 {
-   p->current->header.saturate = enable;
+   brw_inst_set_saturate(p->brw, p->current, enable);
 }
 
 void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
@@ -163,7 +163,7 @@ void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
    struct brw_context *brw = p->brw;
 
    if (brw->gen >= 6)
-      p->current->header.acc_wr_control = value;
+      brw_inst_set_acc_wr_control(p->brw, p->current, value);
 }
 
 void brw_push_insn_state( struct brw_compile *p )
@@ -240,10 +240,10 @@ brw_disassemble(struct brw_context *brw,
    for (int offset = start; offset < end;) {
       struct brw_instruction *insn = assembly + offset;
       struct brw_instruction uncompacted;
-      bool compacted = insn->header.cmpt_control;
+      bool compacted = brw_inst_cmpt_control(brw, insn);
       fprintf(out, "0x%08x: ", offset);
 
-      if (insn->header.cmpt_control) {
+      if (compacted) {
 	 struct brw_compact_instruction *compacted = (void *)insn;
 	 if (dump_hex) {
 	    fprintf(out, "0x%08x 0x%08x                       ",
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 9f1a5fd..84f293e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -34,6 +34,7 @@
 #define BRW_EU_H
 
 #include <stdbool.h>
+#include "brw_inst.h"
 #include "brw_structs.h"
 #include "brw_defines.h"
 #include "brw_reg.h"
@@ -434,7 +435,7 @@ next_offset(const struct brw_context *brw, void *store, int offset)
    struct brw_instruction *insn =
       (struct brw_instruction *)((char *)store + offset);
 
-   if (insn->header.cmpt_control)
+   if (brw_inst_cmpt_control(brw, insn))
       return offset + 8;
    else
       return offset + 16;
-- 
1.8.3.2