[Mesa-dev] [PATCH 2/2] i965/vec4: Fix dead code elimination for VGRFs of size > 1.

[Kenneth Graunke]

When faced with code such as:

    mov vgrf31.0:UD, 960D
    mov vgrf31.1:UD, vgrf30.xxxx:UD

The dead code eliminator brilliantly decided that the second instruction
was writing to the same register as the first one, so the first one
could be eliminated.  Except that they're not the same register at all.

This fixes INTEL_DEBUG=shader_time for vertex shaders.  In the above
code, vgrf31.0 represents the offset into the shader_time buffer where
the data should be written, and vgrf31.1 represents the actual time
data.  With a completely undefined offset, results were...unexpected.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79029
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
Cc: Eero Tamminen <eero.t.tamminen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index e816b94..ee5be56 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -464,7 +464,8 @@ vec4_visitor::dead_code_eliminate()
          }
 
          if (inst->dst.file == scan_inst->dst.file &&
-             inst->dst.reg == scan_inst->dst.reg) {
+             inst->dst.reg == scan_inst->dst.reg &&
+             inst->dst.reg_offset == scan_inst->dst.reg_offset) {
             int new_writemask = scan_inst->dst.writemask & ~dead_channels;
 
             progress = try_eliminate_instruction(scan_inst, new_writemask, brw) ||
-- 
2.0.0