[Mesa-dev] [PATCH 1/6] i965: Add auxiliary surface field #defines for Broadwell.

[Kenneth Graunke]

From: Jordan Justen <jordan.l.justen at intel.com>

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_defines.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

Sending these out mostly as a formality - Jordan and I already reviewed
each other's work.  But, in case anyone spots anything funny...

Available as 'cms-v2' of ~kwg/mesa.

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index a962c7b..8dfe87e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -580,6 +580,16 @@
 #define GEN7_SURFACE_MCS_ENABLE                 (1 << 0)
 #define GEN7_SURFACE_MCS_PITCH_SHIFT            3
 #define GEN7_SURFACE_MCS_PITCH_MASK             INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_QPITCH_SHIFT           16
+#define GEN8_SURFACE_AUX_QPITCH_MASK            INTEL_MASK(30, 16)
+#define GEN8_SURFACE_AUX_PITCH_SHIFT            3
+#define GEN8_SURFACE_AUX_PITCH_MASK             INTEL_MASK(11, 3)
+#define GEN8_SURFACE_AUX_MODE_MASK              INTEL_MASK(2, 0)
+
+#define GEN8_SURFACE_AUX_MODE_NONE              0
+#define GEN8_SURFACE_AUX_MODE_MCS               1
+#define GEN8_SURFACE_AUX_MODE_APPEND            2
+#define GEN8_SURFACE_AUX_MODE_HIZ               3
 
 /* Surface state DW7 */
 #define GEN7_SURFACE_CLEAR_COLOR_SHIFT		28
-- 
2.0.0