[Mesa-dev] [PATCH 12/23] i965/disasm: Actually disassemble Gen7+ URB opcodes.
Kenneth Graunke
kenneth at whitecape.org
Sat Jun 28 21:33:51 PDT 2014
I never bothered implementing the disassembler for Gen7+ URB opcodes, so
we were just disassembling them as Ironlake/Sandybridge ones. This
looked pretty bad when running Paul's GS EndPrimitive tests, as the
"write OWord" message was decoded at ff_sync, which doesn't exist.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_disasm.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 14cb687..4e75cc7 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -478,11 +478,24 @@ static const char *const math_precision[2] = {
[1] = "partial_precision"
};
-static const char *const urb_opcode[2] = {
+static const char *const gen5_urb_opcode[] = {
[0] = "urb_write",
[1] = "ff_sync",
};
+static const char *const gen7_urb_opcode[] = {
+ [0] = "write HWord",
+ [1] = "write OWord",
+ [2] = "read HWord",
+ [3] = "read OWord",
+ [4] = "atomic mov", /* Gen7+ */
+ [5] = "atomic inc", /* Gen7+ */
+ [6] = "atomic add", /* Gen8+ */
+ [7] = "SIMD8 write", /* Gen8+ */
+ [8] = "SIMD8 read", /* Gen8+ */
+ /* [9-15] - reserved */
+};
+
static const char *const urb_swizzle[4] = {
[BRW_URB_SWIZZLE_NONE] = "",
[BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
@@ -1361,8 +1374,11 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
format(file, " %d", brw_inst_urb_global_offset(brw, inst));
space = 1;
- if (brw->gen >= 5) {
- err |= control(file, "urb opcode", urb_opcode,
+ if (brw->gen >= 7) {
+ err |= control(file, "urb opcode", gen7_urb_opcode,
+ brw_inst_urb_opcode(brw, inst), &space);
+ } else if (brw->gen >= 5) {
+ err |= control(file, "urb opcode", gen5_urb_opcode,
brw_inst_urb_opcode(brw, inst), &space);
}
err |= control(file, "urb swizzle", urb_swizzle,
--
2.0.0
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