[Mesa-dev] [PATCH 03/13] i965: Make a common backend_reg class.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_fs.h                 | 24 +---------------
 src/mesa/drivers/dri/i965/brw_shader.h             | 32 ++++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_vec4.h               | 20 ++------------
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp     |  2 +-
 4 files changed, 36 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index c32b0a6..b6a5717 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -63,7 +63,7 @@ namespace brw {
    class fs_live_variables;
 }
 
-class fs_reg {
+class fs_reg : public backend_reg {
 public:
    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
 
@@ -90,36 +90,14 @@ public:
    /** Smear a channel of the reg to all channels. */
    fs_reg &set_smear(unsigned subreg);
 
-   /** Register file: GRF, MRF, IMM. */
-   enum register_file file;
-   /** Register type.  BRW_REGISTER_TYPE_* */
-   uint8_t type;
-   /**
-    * Register number.  For MRF, it's the hardware register.  For
-    * GRF, it's a virtual register number until register allocation
-    */
-   uint16_t reg;
-   /**
-    * Offset from the start of the contiguous register block.
-    *
-    * For pre-register-allocation GRFs, this is in units of a float per pixel
-    * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
-    * For uniforms, this is in units of 1 float.
-    */
-   int reg_offset;
    /**
     * Offset in bytes from the start of the register.  Values up to a
     * backend_reg::reg_offset unit are valid.
     */
    int subreg_offset;
 
-   struct brw_reg fixed_hw_reg;
-
    fs_reg *reladdr;
 
-   bool negate;
-   bool abs;
-
    /** Register region horizontal stride */
    uint8_t stride;
 };
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index e602bcd..3896442 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -22,6 +22,7 @@
  */
 
 #include <stdint.h>
+#include "brw_reg.h"
 #include "brw_defines.h"
 #include "main/compiler.h"
 #include "glsl/ir.h"
@@ -39,6 +40,37 @@ enum PACKED register_file {
    UNIFORM, /* prog_data->params[reg] */
 };
 
+struct backend_reg
+{
+   enum register_file file; /**< Register file: GRF, MRF, IMM. */
+   uint8_t type;            /**< Register type: BRW_REGISTER_TYPE_* */
+
+   /**
+    * Register number.
+    *
+    * For GRF, it's a virtual register number until register allocation.
+    *
+    * For MRF, it's the hardware register.
+    */
+   uint16_t reg;
+
+   /**
+    * Offset within the virtual register.
+    *
+    * In the scalar backend, this is in units of a float per pixel for pre-
+    * register allocation registers (i.e., one register in SIMD8 mode and two
+    * registers in SIMD16 mode).
+    *
+    * For uniforms, this is in units of 1 float.
+    */
+   int reg_offset;
+
+   struct brw_reg fixed_hw_reg;
+
+   bool negate;
+   bool abs;
+};
+
 #ifdef __cplusplus
 
 class cfg_t;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 9a5b1cb..9fd14f8 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -91,21 +91,7 @@ class dst_reg;
 unsigned
 swizzle_for_size(int size);
 
-class reg
-{
-public:
-   /** Register file: GRF, MRF, IMM. */
-   enum register_file file;
-   /** virtual register number.  0 = fixed hw reg */
-   int reg;
-   /** Offset within the virtual register. */
-   int reg_offset;
-   /** Register type.  BRW_REGISTER_TYPE_* */
-   int type;
-   struct brw_reg fixed_hw_reg;
-};
-
-class src_reg : public reg
+class src_reg : public backend_reg
 {
 public:
    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
@@ -129,8 +115,6 @@ public:
    explicit src_reg(dst_reg reg);
 
    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
-   bool negate;
-   bool abs;
 
    src_reg *reladdr;
 };
@@ -174,7 +158,7 @@ negate(src_reg reg)
    return reg;
 }
 
-class dst_reg : public reg
+class dst_reg : public backend_reg
 {
 public:
    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 4ffc537..1caf5ab 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -34,7 +34,7 @@ using namespace brw;
 namespace brw {
 
 static void
-assign(unsigned int *reg_hw_locations, reg *reg)
+assign(unsigned int *reg_hw_locations, backend_reg *reg)
 {
    if (reg->file == GRF) {
       reg->reg = reg_hw_locations[reg->reg];
-- 
1.8.3.2