[Mesa-dev] [RFC PATCH 2/5] i965/vec4: Add support for the MAC instruction.

[Juha-Pekka Heikkila]

This allows us to generate the MAC (multiply-accumulate) instruction,
which can be used to implement some expressions in fewer instructions
than doing a series of MUL and ADDs.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
---
 src/mesa/drivers/dri/i965/brw_eu.h               | 1 +
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 3 +++
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   | 1 +
 3 files changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 5df6bb7..f10ad50 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -183,6 +183,7 @@ ALU1(FBL)
 ALU1(CBIT)
 ALU2(ADDC)
 ALU2(SUBB)
+ALU2(MAC)
 
 ROUND(RNDZ)
 ROUND(RNDE)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 5f85d31..bcacde9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1081,6 +1081,9 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       assert(brw->gen >= 7);
       brw_SUBB(p, dst, src[0], src[1]);
       break;
+   case BRW_OPCODE_MAC:
+      brw_MAC(p, dst, src[0], src[1]);
+      break;
 
    case BRW_OPCODE_BFE:
       assert(brw->gen >= 7);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 33df5d3..aa807e4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -175,6 +175,7 @@ ALU1(CBIT)
 ALU3(MAD)
 ALU2_ACC(ADDC)
 ALU2_ACC(SUBB)
+ALU2(MAC)
 
 /** Gen4 predicated IF. */
 vec4_instruction *
-- 
1.8.1.2