[Mesa-dev] [PATCH] i965: Drop BLT TexSubImage Y-tiling restriction on Gen6+.

[Anuj Phogat]

On Thu, Mar 20, 2014 at 4:02 PM, Kenneth Graunke <kenneth at whitecape.org> wrote:
> Currently, we don't use this path on Sandybridge because we suspect
> other paths will be faster.  But we potentially could.  If we do, we
> should allow it to support Y-tiled BLTs.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/intel_tex_subimage.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> index 6942039..b65a772 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> @@ -98,8 +98,8 @@ intel_blit_texsubimage(struct gl_context * ctx,
>     if (!intelImage->mt)
>        return false;
>
> -   /* The blitter can't handle Y tiling */
> -   if (intelImage->mt->region->tiling == I915_TILING_Y)
> +   /* Prior to Sandybridge, the blitter can't handle Y tiling */
> +   if (brw->gen < 6 && intelImage->mt->region->tiling == I915_TILING_Y)
>        return false;
>
>     if (texImage->TexObject->Target != GL_TEXTURE_2D)
> --
> 1.9.0
>
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Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>