[Mesa-dev] [PATCH 2/2] i965/vec4: Simulate MAD opcode for gen<6

Juha-Pekka Heikkila juhapekka.heikkila at gmail.com
Tue May 6 03:53:59 PDT 2014


Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
---
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 41 ++++++++++++++++++--------
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 7bad81c..506a4b2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1092,10 +1092,6 @@ vec4_visitor::try_emit_sat(ir_expression *ir)
 bool
 vec4_visitor::try_emit_mad(ir_expression *ir)
 {
-   /* 3-src instructions were introduced in gen6. */
-   if (brw->gen < 6)
-      return false;
-
    /* MAD can only handle floating-point data. */
    if (ir->type->base_type != GLSL_TYPE_FLOAT)
       return false;
@@ -1111,17 +1107,38 @@ vec4_visitor::try_emit_mad(ir_expression *ir)
          return false;
    }
 
-   nonmul->accept(this);
-   src_reg src0 = fix_3src_operand(this->result);
+   /* 3-src instructions were introduced in gen6. */
+   if (brw->gen < 6) {
+      nonmul->accept(this);
+      src_reg src0(this->result);
 
-   mul->operands[0]->accept(this);
-   src_reg src1 = fix_3src_operand(this->result);
+      mul->operands[0]->accept(this);
+      src_reg src1(this->result);
 
-   mul->operands[1]->accept(this);
-   src_reg src2 = fix_3src_operand(this->result);
+      mul->operands[1]->accept(this);
+      src_reg src2(this->result);
 
-   this->result = src_reg(this, ir->type);
-   emit(BRW_OPCODE_MAD, dst_reg(this->result), src0, src1, src2);
+      this->result = src_reg(this, ir->type);
+
+      dst_reg mul_destination = dst_reg(this, glsl_type::float_type);
+      mul_destination.writemask = dst_reg(this->result).writemask;
+
+      emit(MUL(mul_destination, src1, src2));
+      emit(ADD(dst_reg(this->result), src0, src_reg(mul_destination)));
+   } else {
+      nonmul->accept(this);
+      src_reg src0 = fix_3src_operand(this->result);
+
+      mul->operands[0]->accept(this);
+      src_reg src1 = fix_3src_operand(this->result);
+
+      mul->operands[1]->accept(this);
+      src_reg src2 = fix_3src_operand(this->result);
+
+      this->result = src_reg(this, ir->type);
+
+      emit(BRW_OPCODE_MAD, dst_reg(this->result), src0, src1, src2);
+   }
 
    return true;
 }
-- 
1.8.1.2



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