[Mesa-dev] [rong.r.yang at intel.com: [Intel-gfx] How user space applications load registers on HSW?]

[Ben Widawsky]

FWDing to mesa-dev, since they should have the same issue.

----- Forwarded message from "Yang, Rong R" <rong.r.yang at intel.com> -----

Date: Tue, 6 May 2014 08:26:15 +0000
From: "Yang, Rong R" <rong.r.yang at intel.com>
To: "intel-gfx at lists.freedesktop.org" <intel-gfx at lists.freedesktop.org>
Subject: [Intel-gfx] How user space applications load registers on HSW?
Message-ID: <7597C9376C272A4AB2D29E91550B7B090135408C at shsmsx102.ccr.corp.intel.com>

   Hi,


   I am developing the HSW’s OCL driver in the linux. I encounter a LRI
   problem on HSW.


   Some gpgpu's applications, which use the shared local memory, must load
   the L3CTRLREG2 and L3CTRLREG3 registers to allocate the SLM in the L3
   cache.

   So I add L3CTRLREG2 and L3CTRLREG3 to the gen7_render_regs to pass the
   cmds parse when exec buffer. But it still don’t work.

   I notice that, on HSW, the commands that load the register, such as
   MI_LOAD_REGISTER_IMM, will be converted to NOOP by the GPU if the batch
   buffer's MI_BATCH_NON_SECURE_HSW bit is set. And after parse cmd, the
   MI_BATCH_NON_SECURE_HSW still set in the kernel. So HSW don’t accept
   LRI commands.


   Can I load these registers in the user space? Or should I hack the
   kernel?


   Yang Rong

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----- End forwarded message -----

-- 
Ben Widawsky, Intel Open Source Technology Center