[Mesa-dev] [PATCH 1/2] i965: Generalize the pixel_x/y workaround for all UW types.

[Eric Anholt]

This is the only case where a fs_reg in brw_fs_visitor is used during
optimization/code generation, and it meant that optimizations had to be
careful to not move pixel_x/y's register number without updating it.

Additionally, it turns out we had a couple of other UW values that weren't
getting this treatment (like gl_SampleID), so this more general fix is
probably a good idea (though I wasn't able to replicate problems with
either pixel_[xy]'s values or gl_SampleID, even when telling the register
allocator to reuse registers immediately)
---
 src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index c7b1f25..7969b67 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
@@ -86,10 +86,10 @@ fs_live_variables::setup_one_read(bblock_t *block, fs_inst *inst,
     */
    int end_ip = ip;
    if (v->dispatch_width == 16 && (reg.stride == 0 ||
-                                   ((v->pixel_x.file == GRF &&
-                                     v->pixel_x.reg == reg.reg) ||
-                                    (v->pixel_y.file == GRF &&
-                                     v->pixel_y.reg == reg.reg)))) {
+                                   reg.type == BRW_REGISTER_TYPE_UW ||
+                                   reg.type == BRW_REGISTER_TYPE_W ||
+                                   reg.type == BRW_REGISTER_TYPE_UB ||
+                                   reg.type == BRW_REGISTER_TYPE_B)) {
       end_ip++;
    }
 
-- 
1.9.2