[Mesa-dev] [PATCH 02/13] i965/wm: Surface state overrides for configuring w-tiled as y-tiled

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h            |  6 ++++++
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 ++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index b8e8520..dbcf7c7 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -206,6 +206,12 @@ void gen4_init_vtable_surface_functions(struct brw_context *brw);
 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
 
+void brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
+                           bool is_render_target,
+                           unsigned *width, unsigned *height,
+                           unsigned *pitch, uint32_t *tiling,
+                           unsigned *format);
+
 uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
 
 GLuint translate_tex_target(GLenum target);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 054467c..f400c41 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -101,6 +101,28 @@ brw_get_surface_num_multisamples(unsigned num_samples)
       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 }
 
+void
+brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
+                      bool is_render_target,
+                      unsigned *width, unsigned *height,
+                      unsigned *pitch, uint32_t *tiling, unsigned *format)
+{
+   const unsigned x_align = 8, y_align = mt->num_samples != 0 ? 8 : 4;
+
+   *tiling = I915_TILING_Y;
+   *pitch = mt->pitch * 2;
+   *width = ALIGN(mt->physical_width0, x_align) * 2;
+   *height = ALIGN(mt->physical_height0, y_align) / 2;
+
+   /* Allow program to access pixels in any mip-level */
+   if (mt->last_level > 1)
+      *height *= 2;
+
+   if (is_render_target) {
+      *format = BRW_SURFACEFORMAT_R8_UINT;
+   }
+}
+
 
 /**
  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
-- 
1.8.3.1