[Mesa-dev] [PATCH] radeonsi: Implement DMA blit for CIK (wip)
Alex Deucher
alexdeucher at gmail.com
Fri May 23 07:12:53 PDT 2014
This implements blit support using the partial blit
packets which properly handle subwindow blits. linear
<-> tiled blits aren't quite right and cause GPU page
faults in certain cases.
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
src/gallium/drivers/radeonsi/Makefile.sources | 1 +
src/gallium/drivers/radeonsi/cik_dma.c | 487 ++++++++++++++++++++++++++
src/gallium/drivers/radeonsi/si_dma.c | 15 -
src/gallium/drivers/radeonsi/si_pipe.h | 9 +
src/gallium/drivers/radeonsi/si_state.c | 21 +-
src/gallium/drivers/radeonsi/si_state.h | 1 +
6 files changed, 518 insertions(+), 16 deletions(-)
create mode 100644 src/gallium/drivers/radeonsi/cik_dma.c
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources b/src/gallium/drivers/radeonsi/Makefile.sources
index 6a24cde..9e343f5 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -4,6 +4,7 @@ C_SOURCES := \
si_compute.c \
si_descriptors.c \
si_dma.c \
+ cik_dma.c \
si_hw_context.c \
si_pipe.c \
si_pm4.c \
diff --git a/src/gallium/drivers/radeonsi/cik_dma.c b/src/gallium/drivers/radeonsi/cik_dma.c
new file mode 100644
index 0000000..d766ebf
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/cik_dma.c
@@ -0,0 +1,487 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse at freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Jerome Glisse
+ */
+
+#include "sid.h"
+#include "si_pipe.h"
+#include "../radeon/r600_cs.h"
+
+#include "util/u_format.h"
+
+#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
+ (((sub_op) & 0xFF) << 8) | \
+ (((op) & 0xFF) << 0))
+
+/* sDMA opcodes */
+#define SDMA_OPCODE_NOP 0
+#define SDMA_OPCODE_COPY 1
+# define SDMA_COPY_SUB_OPCODE_LINEAR 0
+# define SDMA_COPY_SUB_OPCODE_TILED 1
+# define SDMA_COPY_SUB_OPCODE_SOA 3
+# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
+# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
+# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
+/* copy extra bits */
+# define SDMA_COPY_TILED_EXTRA_DETILE (1 << 15)
+#define SDMA_OPCODE_WRITE 2
+# define SDMA_WRITE_SUB_OPCODE_LINEAR 0
+# define SDMA_WRTIE_SUB_OPCODE_TILED 1
+
+#define CIK_DMA_COPY_LINEAR_MAX_SIZE_BYTES 0x1fffff
+#define CIK_DMA_COPY_TILED_MAX_SIZE_DW 0xfffff
+
+static uint32_t cik_micro_tile_mode(struct si_screen *sscreen, unsigned tile_mode)
+{
+ if (sscreen->b.info.si_tile_mode_array_valid) {
+ uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
+
+ return G_009910_MICRO_TILE_MODE(gb_tile_mode);
+ }
+
+ /* The kernel cannod return the tile mode array. Guess? */
+ return V_009910_ADDR_SURF_THIN_MICRO_TILING;
+}
+
+static void cik_dma_copy_buffer(struct si_context *ctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src,
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
+{
+ struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
+ unsigned i, ncopy, csize;
+ struct r600_resource *rdst = (struct r600_resource*)dst;
+ struct r600_resource *rsrc = (struct r600_resource*)src;
+
+ /* Mark the buffer range of destination as valid (initialized),
+ * so that transfer_map knows it should wait for the GPU when mapping
+ * that range. */
+ util_range_add(&rdst->valid_buffer_range, dst_offset,
+ dst_offset + size);
+
+ dst_offset += r600_resource_va(&ctx->screen->b.b, dst);
+ src_offset += r600_resource_va(&ctx->screen->b.b, src);
+
+ ncopy = (size / CIK_DMA_COPY_LINEAR_MAX_SIZE_BYTES) +
+ !!(size % CIK_DMA_COPY_LINEAR_MAX_SIZE_BYTES);
+
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
+ RADEON_PRIO_MIN);
+
+ r600_need_dma_space(&ctx->b, ncopy * 7);
+ for (i = 0; i < ncopy; i++) {
+ csize = size < CIK_DMA_COPY_LINEAR_MAX_SIZE_BYTES ?
+ size : CIK_DMA_COPY_LINEAR_MAX_SIZE_BYTES;
+ cs->buf[cs->cdw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
+ SDMA_COPY_SUB_OPCODE_LINEAR, 0);
+ cs->buf[cs->cdw++] = csize;
+ cs->buf[cs->cdw++] = 0;
+ cs->buf[cs->cdw++] = src_offset & 0xffffffff;
+ cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xffffffff;
+ cs->buf[cs->cdw++] = dst_offset & 0xffffffff;
+ cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xffffffff;
+
+ dst_offset += csize;
+ src_offset += csize;
+ size -= csize;
+ }
+}
+
+static void cik_dma_copy_l2l_subwindow(struct si_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dst_x,
+ unsigned dst_y,
+ unsigned dst_z,
+ unsigned dst_pitch,
+ struct pipe_resource *src,
+ unsigned src_level,
+ unsigned src_x,
+ unsigned src_y,
+ unsigned src_z,
+ unsigned src_pitch,
+ const struct pipe_box *src_box,
+ unsigned bpp)
+{
+ struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
+ struct r600_texture *rsrc = (struct r600_texture*)src;
+ struct r600_texture *rdst = (struct r600_texture*)dst;
+ uint64_t src_addr, dst_addr;
+ uint32_t src_slice, dst_slice, extra;
+ uint32_t w, h, d;
+ uint32_t linear_src_pitch, linear_dst_pitch;
+
+ extra = util_logbase2(bpp) << 13;
+
+ src_addr = rsrc->surface.level[src_level].offset;
+ dst_addr = rdst->surface.level[dst_level].offset;
+ src_addr += r600_resource_va(&ctx->screen->b.b, src);
+ dst_addr += r600_resource_va(&ctx->screen->b.b, dst);
+
+ linear_src_pitch = (src_pitch / bpp) - 1;
+ linear_dst_pitch = (dst_pitch / bpp) - 1;
+ src_slice = rsrc->surface.level[src_level].npix_y * src_pitch;
+ dst_slice = rdst->surface.level[dst_level].npix_y * dst_pitch;
+
+ w = src_box->width;
+ h = src_box->height;
+ d = src_box->depth;
+
+ r600_need_dma_space(&ctx->b, 13);
+
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
+
+ cs->buf[cs->cdw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
+ SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, extra);
+ cs->buf[cs->cdw++] = src_addr & 0xfffffffff;
+ cs->buf[cs->cdw++] = (src_addr >> 32UL) & 0xffffffff;
+ cs->buf[cs->cdw++] = (src_x << 0) | (src_y << 16);
+ cs->buf[cs->cdw++] = (src_z << 0) | (linear_src_pitch << 16);
+ cs->buf[cs->cdw++] = (src_slice << 0);
+ cs->buf[cs->cdw++] = dst_addr & 0xffffffff;
+ cs->buf[cs->cdw++] = (dst_addr >> 32UL) & 0xffffffff;
+ cs->buf[cs->cdw++] = (dst_x << 0) | (dst_y << 16);
+ cs->buf[cs->cdw++] = (dst_z << 0) | (linear_dst_pitch << 16);
+ cs->buf[cs->cdw++] = (dst_slice << 0);
+ cs->buf[cs->cdw++] = (w << 0) | (h << 16);
+ cs->buf[cs->cdw++] = (d << 0);
+}
+
+static void cik_dma_copy_t2t_subwindow(struct si_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dst_x,
+ unsigned dst_y,
+ unsigned dst_z,
+ unsigned dst_pitch,
+ struct pipe_resource *src,
+ unsigned src_level,
+ unsigned src_x,
+ unsigned src_y,
+ unsigned src_z,
+ unsigned src_pitch,
+ const struct pipe_box *src_box,
+ unsigned bpp)
+{
+ struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
+ struct si_screen *sscreen = ctx->screen;
+ struct r600_texture *rsrc = (struct r600_texture*)src;
+ struct r600_texture *rdst = (struct r600_texture*)dst;
+ uint32_t src_array_mode, src_pitch_tile, src_slice_tile, src_mode;
+ unsigned src_bank_h, src_bank_w, src_mt_aspect, src_nbanks, src_tile_split;
+ unsigned src_pipe_config, src_tile_mode_index, src_mt;
+ uint64_t src_addr;
+ uint32_t dst_array_mode, dst_pitch_tile, dst_slice_tile, dst_mode;
+ unsigned dst_bank_h, dst_bank_w, dst_mt_aspect, dst_nbanks, dst_tile_split;
+ unsigned dst_pipe_config, dst_tile_mode_index, dst_mt;
+ uint64_t dst_addr;
+ uint32_t lbpp, w, h, d;
+
+ dst_mode = rdst->surface.level[dst_level].mode;
+ src_mode = rsrc->surface.level[src_level].mode;
+
+ lbpp = util_logbase2(bpp);
+
+ w = src_box->width;
+ h = src_box->height;
+ d = src_box->depth;
+
+ /* src */
+ src_pitch_tile = ((src_pitch / bpp) / 8) - 1;
+ src_array_mode = si_array_mode(src_mode);
+ src_slice_tile = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
+ src_slice_tile = src_slice_tile ? src_slice_tile - 1 : 0;
+ src_addr = rsrc->surface.level[src_level].offset;
+ src_bank_h = cik_bank_wh(rsrc->surface.bankh);
+ src_bank_w = cik_bank_wh(rsrc->surface.bankw);
+ src_mt_aspect = cik_macro_tile_aspect(rsrc->surface.mtilea);
+ src_tile_split = cik_tile_split(rsrc->surface.tile_split);
+ src_tile_mode_index = si_tile_mode_index(rsrc, src_level,
+ util_format_has_stencil(util_format_description(src->format)));
+ src_nbanks = si_num_banks(sscreen, rsrc->surface.bpe, rsrc->surface.tile_split,
+ src_tile_mode_index);
+ src_addr += r600_resource_va(&ctx->screen->b.b, src);
+ src_pipe_config = cik_db_pipe_config(sscreen, src_tile_mode_index);
+ src_mt = cik_micro_tile_mode(sscreen, src_tile_mode_index);
+
+ /* dst */
+ dst_pitch_tile = ((dst_pitch / bpp) / 8) - 1;
+ dst_array_mode = si_array_mode(dst_mode);
+ dst_slice_tile = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
+ dst_slice_tile = dst_slice_tile ? dst_slice_tile - 1 : 0;
+ dst_addr = rdst->surface.level[dst_level].offset;
+ dst_bank_h = cik_bank_wh(rdst->surface.bankh);
+ dst_bank_w = cik_bank_wh(rdst->surface.bankw);
+ dst_mt_aspect = cik_macro_tile_aspect(rdst->surface.mtilea);
+ dst_tile_split = cik_tile_split(rdst->surface.tile_split);
+ dst_tile_mode_index = si_tile_mode_index(rdst, dst_level,
+ util_format_has_stencil(util_format_description(dst->format)));
+ dst_nbanks = si_num_banks(sscreen, rdst->surface.bpe, rdst->surface.tile_split,
+ dst_tile_mode_index);
+ dst_addr += r600_resource_va(&ctx->screen->b.b, dst);
+ dst_pipe_config = cik_db_pipe_config(sscreen, dst_tile_mode_index);
+ dst_mt = cik_micro_tile_mode(sscreen, dst_tile_mode_index);
+
+ r600_need_dma_space(&ctx->b, 15);
+
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
+
+ cs->buf[cs->cdw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
+ SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0);
+ cs->buf[cs->cdw++] = src_addr & 0xfffffff00;
+ cs->buf[cs->cdw++] = (src_addr >> 32UL) & 0xffffffff;
+ cs->buf[cs->cdw++] = (src_x << 0) | (src_y << 16);
+ cs->buf[cs->cdw++] = (src_z << 0) | (src_pitch_tile << 16);
+ cs->buf[cs->cdw++] = (src_slice_tile << 0);
+ cs->buf[cs->cdw++] = ((src_pipe_config << 26) | (src_mt_aspect << 24) |
+ (src_nbanks << 21) | (src_bank_h << 18) |
+ (src_bank_w << 15) | (src_tile_split << 11) |
+ (src_mt << 8) | (src_array_mode << 3) | (lbpp << 0));
+ cs->buf[cs->cdw++] = dst_addr & 0xffffff00;
+ cs->buf[cs->cdw++] = (dst_addr >> 32UL) & 0xffffffff;
+ cs->buf[cs->cdw++] = (dst_x << 0) | (dst_y << 16);
+ cs->buf[cs->cdw++] = (dst_z << 0) | (dst_pitch_tile << 16);
+ cs->buf[cs->cdw++] = (dst_slice_tile << 0);
+ cs->buf[cs->cdw++] = ((dst_pipe_config << 26) | (dst_mt_aspect << 24) |
+ (dst_nbanks << 21) | (dst_bank_h << 18) |
+ (dst_bank_w << 15) | (dst_tile_split << 11) |
+ (dst_mt << 8) | (dst_array_mode << 3) | (lbpp << 0));
+ cs->buf[cs->cdw++] = (w << 0) | (h << 16);
+ cs->buf[cs->cdw++] = (d << 0);
+}
+
+static void cik_dma_copy_l2t_t2l_subwindow(struct si_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dst_x,
+ unsigned dst_y,
+ unsigned dst_z,
+ unsigned dst_pitch,
+ struct pipe_resource *src,
+ unsigned src_level,
+ unsigned src_x,
+ unsigned src_y,
+ unsigned src_z,
+ unsigned src_pitch,
+ const struct pipe_box *src_box,
+ unsigned bpp)
+{
+ struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
+ struct si_screen *sscreen = ctx->screen;
+ struct r600_texture *rsrc = (struct r600_texture*)src;
+ struct r600_texture *rdst = (struct r600_texture*)dst;
+ uint32_t array_mode, lbpp, pitch_tile, slice_tile;
+ uint32_t src_mode, dst_mode;
+ uint32_t bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
+ uint64_t tiled_addr, linear_addr;
+ uint32_t pipe_config, tile_mode_index, extra;
+ uint32_t tiled_x, tiled_y, tiled_z;
+ uint32_t linear_x, linear_y, linear_z;
+ uint32_t linear_pitch, linear_slice;
+ uint32_t w, h, d;
+
+ dst_mode = rdst->surface.level[dst_level].mode;
+ src_mode = rsrc->surface.level[src_level].mode;
+ /* downcast linear aligned to linear to simplify test */
+ src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
+ dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
+ assert(dst_mode != src_mode);
+
+ w = src_box->width;
+ h = src_box->height;
+ d = src_box->depth;
+
+ lbpp = util_logbase2(bpp);
+
+ if (dst_mode == RADEON_SURF_MODE_LINEAR) {
+ /* T2L */
+ extra = SDMA_COPY_TILED_EXTRA_DETILE;
+ array_mode = si_array_mode(src_mode);
+ pitch_tile = ((src_pitch / bpp) / 8) - 1;
+ slice_tile = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
+ slice_tile = slice_tile ? slice_tile - 1 : 0;
+ linear_pitch = (dst_pitch / bpp) - 1;
+ linear_slice = (rdst->surface.level[dst_level].npix_y * (dst_pitch / bpp)) - 1;
+ tiled_addr = rsrc->surface.level[src_level].offset;
+ linear_addr = rdst->surface.level[dst_level].offset;
+ bank_h = cik_bank_wh(rsrc->surface.bankh);
+ bank_w = cik_bank_wh(rsrc->surface.bankw);
+ mt_aspect = cik_macro_tile_aspect(rsrc->surface.mtilea);
+ tile_split = cik_tile_split(rsrc->surface.tile_split);
+ tile_mode_index = si_tile_mode_index(rsrc, src_level,
+ util_format_has_stencil(util_format_description(src->format)));
+ nbanks = si_num_banks(sscreen, rsrc->surface.bpe, rsrc->surface.tile_split,
+ tile_mode_index);
+ tiled_addr += r600_resource_va(&ctx->screen->b.b, src);
+ linear_addr += r600_resource_va(&ctx->screen->b.b, dst);
+ tiled_x = src_x;
+ tiled_y = src_y;
+ tiled_z = src_z;
+ linear_x = dst_x;
+ linear_y = dst_y;
+ linear_z = dst_z;
+ } else {
+ /* L2T */
+ extra = 0;
+ array_mode = si_array_mode(dst_mode);
+ pitch_tile = ((dst_pitch / bpp) / 8) - 1;
+ slice_tile = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
+ slice_tile = slice_tile ? slice_tile - 1 : 0;
+ linear_pitch = (src_pitch / bpp) - 1;
+ linear_slice = (rsrc->surface.level[src_level].npix_y * (src_pitch / bpp)) - 1;
+ tiled_addr = rdst->surface.level[dst_level].offset;
+ linear_addr = rsrc->surface.level[src_level].offset;
+ bank_h = cik_bank_wh(rdst->surface.bankh);
+ bank_w = cik_bank_wh(rdst->surface.bankw);
+ mt_aspect = cik_macro_tile_aspect(rdst->surface.mtilea);
+ tile_split = cik_tile_split(rdst->surface.tile_split);
+ tile_mode_index = si_tile_mode_index(rdst, dst_level,
+ util_format_has_stencil(util_format_description(dst->format)));
+ nbanks = si_num_banks(sscreen, rdst->surface.bpe, rdst->surface.tile_split,
+ tile_mode_index);
+ tiled_addr += r600_resource_va(&ctx->screen->b.b, dst);
+ linear_addr += r600_resource_va(&ctx->screen->b.b, src);
+ tiled_x = dst_x;
+ tiled_y = dst_y;
+ tiled_z = dst_z;
+ linear_x = src_x;
+ linear_y = src_y;
+ linear_z = src_z;
+ }
+
+ pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
+ mt = cik_micro_tile_mode(sscreen, tile_mode_index);
+
+ r600_need_dma_space(&ctx->b, 14);
+
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
+
+ cs->buf[cs->cdw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
+ SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, extra);
+ cs->buf[cs->cdw++] = tiled_addr & 0xffffff00;
+ cs->buf[cs->cdw++] = (tiled_addr >> 32UL) & 0xffffffff;
+ cs->buf[cs->cdw++] = (tiled_x << 0) | (tiled_y << 16);
+ cs->buf[cs->cdw++] = (tiled_z << 0) | (pitch_tile << 16);
+ cs->buf[cs->cdw++] = (slice_tile << 0);
+ cs->buf[cs->cdw++] = ((pipe_config << 26) | (mt_aspect << 24) |
+ (nbanks << 21) | (bank_h << 18) |
+ (bank_w << 15) | (tile_split << 11) |
+ (mt << 8) | (array_mode << 3) | (lbpp << 0));
+ cs->buf[cs->cdw++] = linear_addr & 0xfffffffc;
+ cs->buf[cs->cdw++] = (linear_addr >> 32UL) & 0xffffffff;
+ cs->buf[cs->cdw++] = (linear_x << 0) | (linear_y << 16);
+ cs->buf[cs->cdw++] = (linear_z << 0) | (linear_pitch << 16);
+ cs->buf[cs->cdw++] = (linear_slice << 0);
+ cs->buf[cs->cdw++] = (w << 0) | (h << 16);
+ cs->buf[cs->cdw++] = (d << 0);
+}
+
+void cik_dma_copy(struct pipe_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box)
+{
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct r600_texture *rsrc = (struct r600_texture*)src;
+ struct r600_texture *rdst = (struct r600_texture*)dst;
+ unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode;
+ unsigned src_x, src_y;
+ unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
+
+ if (sctx->b.rings.dma.cs == NULL) {
+ goto fallback;
+ }
+
+ if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
+ cik_dma_copy_buffer(sctx, dst, src, dst_x, src_box->x, src_box->width);
+ return;
+ }
+
+ if (src->format != dst->format ||
+ rdst->dirty_level_mask != 0) {
+ goto fallback;
+ }
+
+ if (rsrc->dirty_level_mask) {
+ ctx->flush_resource(ctx, src);
+ }
+
+ src_x = util_format_get_nblocksx(src->format, src_box->x);
+ dst_x = util_format_get_nblocksx(src->format, dst_x);
+ src_y = util_format_get_nblocksy(src->format, src_box->y);
+ dst_y = util_format_get_nblocksy(src->format, dst_y);
+
+ bpp = rdst->surface.bpe;
+ dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
+ src_pitch = rsrc->surface.level[src_level].pitch_bytes;
+
+ dst_mode = rdst->surface.level[dst_level].mode;
+ src_mode = rsrc->surface.level[src_level].mode;
+ /* downcast linear aligned to linear to simplify test */
+ src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
+ dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
+
+ if ((src_mode == RADEON_SURF_MODE_LINEAR) &&
+ (dst_mode == RADEON_SURF_MODE_LINEAR)) {
+ cik_dma_copy_l2l_subwindow(sctx, dst, dst_level, dst_x, dst_y, dst_z,
+ dst_pitch, src, src_level, src_x, src_y, src_box->z,
+ src_pitch, src_box, bpp);
+ } else if ((src_mode != RADEON_SURF_MODE_LINEAR) &&
+ (dst_mode != RADEON_SURF_MODE_LINEAR)) {
+ /* coordinates must be a tile multiple */
+ if ((src_x % 8) || (dst_x % 8) || (src_y % 8) || (dst_y % 8))
+ goto fallback;
+ cik_dma_copy_t2t_subwindow(sctx, dst, dst_level, dst_x, dst_y, dst_z,
+ dst_pitch, src, src_level, src_x, src_y, src_box->z,
+ src_pitch, src_box, bpp);
+ } else {
+ /* x and width must be aligned to 1 dword */
+ if (((src_x * bpp) % 4) || ((dst_x * bpp) % 4) || ((src_box->width * bpp) % 4))
+ goto fallback;
+ cik_dma_copy_l2t_t2l_subwindow(sctx, dst, dst_level, dst_x, dst_y, dst_z,
+ dst_pitch, src, src_level, src_x, src_y, src_box->z,
+ src_pitch, src_box, bpp);
+ }
+ return;
+
+fallback:
+ ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
+ src, src_level, src_box);
+}
diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index dc8c609..41a1856 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -30,21 +30,6 @@
#include "util/u_format.h"
-static unsigned si_array_mode(unsigned mode)
-{
- switch (mode) {
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- return V_009910_ARRAY_LINEAR_ALIGNED;
- case RADEON_SURF_MODE_1D:
- return V_009910_ARRAY_1D_TILED_THIN1;
- case RADEON_SURF_MODE_2D:
- return V_009910_ARRAY_2D_TILED_THIN1;
- default:
- case RADEON_SURF_MODE_LINEAR:
- return V_009910_ARRAY_LINEAR_GENERAL;
- }
-}
-
static uint32_t si_micro_tile_mode(struct si_screen *sscreen, unsigned tile_mode)
{
if (sscreen->b.info.si_tile_mode_array_valid) {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index de42477..860e101 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -180,6 +180,15 @@ void si_dma_copy(struct pipe_context *ctx,
unsigned src_level,
const struct pipe_box *src_box);
+/* cik_dma.c */
+void cik_dma_copy(struct pipe_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box);
+
/* si_hw_context.c */
void si_context_gfx_flush(void *context, unsigned flags,
struct pipe_fence_handle **fence);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index e3b72c2..d6fc83e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -47,6 +47,21 @@ static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
*list_elem = atom;
}
+unsigned si_array_mode(unsigned mode)
+{
+ switch (mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED:
+ return V_009910_ARRAY_LINEAR_ALIGNED;
+ case RADEON_SURF_MODE_1D:
+ return V_009910_ARRAY_1D_TILED_THIN1;
+ case RADEON_SURF_MODE_2D:
+ return V_009910_ARRAY_2D_TILED_THIN1;
+ default:
+ case RADEON_SURF_MODE_LINEAR:
+ return V_009910_ARRAY_LINEAR_GENERAL;
+ }
+}
+
uint32_t si_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split,
unsigned tile_mode_index)
{
@@ -3024,7 +3039,11 @@ void si_init_state_functions(struct si_context *sctx)
sctx->b.b.texture_barrier = si_texture_barrier;
sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
- sctx->b.dma_copy = si_dma_copy;
+
+ if (sctx->b.chip_class == CIK)
+ sctx->b.dma_copy = cik_dma_copy;
+ else
+ sctx->b.dma_copy = si_dma_copy;
sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 4c5b09e..36f2580 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -229,6 +229,7 @@ int si_shader_select(struct pipe_context *ctx,
struct si_pipe_shader_selector *sel);
void si_init_state_functions(struct si_context *sctx);
void si_init_config(struct si_context *sctx);
+unsigned si_array_mode(unsigned mode);
unsigned cik_bank_wh(unsigned bankwh);
unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
--
1.8.3.1
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