[Mesa-dev] [PATCH 17/23] i965: Switch types D->UD when possible to allow compaction.

[Eric Anholt]

Matt Turner <mattst88 at gmail.com> writes:

> On Wed, May 21, 2014 at 4:08 PM, Eric Anholt <eric at anholt.net> wrote:
>> Matt Turner <mattst88 at gmail.com> writes:
>>
>>> Number of compacted instructions: 827404 -> 833045 (0.68%)
>>> ---
>>>  src/mesa/drivers/dri/i965/brw_eu_emit.c | 20 ++++++++++++++++++++
>>>  1 file changed, 20 insertions(+)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>>> index 1810233..ab00d7c 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>>> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>>> @@ -295,6 +295,16 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
>>>     /* 10. Check destination issues. */
>>>  }
>>>
>>> +static bool
>>> +is_compactable_immediate(unsigned imm)
>>> +{
>>> +   /* We get the low 12 bits as-is. */
>>> +   imm &= ~0xfff;
>>> +
>>> +   /* We get one bit replicated through the top 20 bits. */
>>> +   return imm == 0 || imm == 0xfffff000;
>>> +}
>>> +
>>>  void
>>>  brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
>>>            struct brw_reg reg)
>>> @@ -373,6 +383,16 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
>>>            insn->bits1.da1.src0_reg_type == BRW_HW_REG_TYPE_F) {
>>>           insn->bits1.da1.src0_reg_type = BRW_HW_REG_IMM_TYPE_VF;
>>>        }
>>> +
>>> +      /* There are no mappings for dst:d | i:d, so if the immediate is suitable
>>> +       * set the types to :UD so the instruction can be compacted.
>>> +       */
>>> +      if (is_compactable_immediate(insn->bits3.ud) &&
>>> +          insn->bits1.da1.src0_reg_type == BRW_HW_REG_TYPE_D &&
>>> +          insn->bits1.da1.dest_reg_type == BRW_HW_REG_TYPE_D) {
>>> +         insn->bits1.da1.src0_reg_type = BRW_HW_REG_TYPE_UD;
>>> +         insn->bits1.da1.dest_reg_type = BRW_HW_REG_TYPE_UD;
>>> +      }
>>
>> Do conditional modifier flags work the same for the same data with D
>> versus UD destinations?  Just trying to come up with cases where
>> changing the type would matter.
>
> I think it'd be different if we did something like
>
> mov.le.f0 dst:D, -1D
>
> and converted it to
>
> mov.le.f0 dst:UD, 0xffffffffUD
>
> you'd get the same bits in dst, but a different value in f0.
>
> I can't imagine we'll ever emit a mov/cmod/immediate-source, but that
> also means we'd never lose anything by disabling it this if there's
> cmod.
>
> I'll change the conditional to include &&
> insn->header.destreg__conditionalmod == 0.
>
> With that fixed, it gets your R-b?

Yeah. (well, with "== BRW_CONDITIONAL_NONE")
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