[Mesa-dev] [PATCH 12/14] i965/fs: Split declarations of fs_reg and fs_inst out of brw_fs.h
Topi Pohjolainen
topi.pohjolainen at intel.com
Wed May 28 05:36:08 PDT 2014
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.h | 174 +------------------------
src/mesa/drivers/dri/i965/brw_fs_emit.h | 220 ++++++++++++++++++++++++++++++++
2 files changed, 221 insertions(+), 173 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_fs_emit.h
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 67dce1e..6c39368 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -51,6 +51,7 @@ extern "C" {
#include "gen8_generator.h"
#include "glsl/glsl_types.h"
#include "glsl/ir.h"
+#include "brw_fs_emit.h"
#define MAX_SAMPLER_MESSAGE_SIZE 11
@@ -63,179 +64,6 @@ namespace brw {
class fs_live_variables;
}
-class fs_reg {
-public:
- DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
-
- void init();
-
- fs_reg();
- fs_reg(float f);
- fs_reg(int32_t i);
- fs_reg(uint32_t u);
- fs_reg(struct brw_reg fixed_hw_reg);
- fs_reg(enum register_file file, int reg);
- fs_reg(enum register_file file, int reg, uint32_t type);
- fs_reg(backend_emitter *e, const struct glsl_type *type);
-
- bool equals(const fs_reg &r) const;
- bool is_zero() const;
- bool is_one() const;
- bool is_null() const;
- bool is_valid_3src() const;
- bool is_contiguous() const;
- bool is_accumulator() const;
-
- fs_reg &apply_stride(unsigned stride);
- /** Smear a channel of the reg to all channels. */
- fs_reg &set_smear(unsigned subreg);
-
- /** Register file: GRF, MRF, IMM. */
- enum register_file file;
- /** Register type. BRW_REGISTER_TYPE_* */
- uint8_t type;
- /**
- * Register number. For MRF, it's the hardware register. For
- * GRF, it's a virtual register number until register allocation
- */
- uint16_t reg;
- /**
- * Offset from the start of the contiguous register block.
- *
- * For pre-register-allocation GRFs, this is in units of a float per pixel
- * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
- * For uniforms, this is in units of 1 float.
- */
- int reg_offset;
- /**
- * Offset in bytes from the start of the register. Values up to a
- * backend_reg::reg_offset unit are valid.
- */
- int subreg_offset;
-
- /** Value for file == IMM */
- union {
- int32_t i;
- uint32_t u;
- float f;
- } imm;
-
- struct brw_reg fixed_hw_reg;
-
- fs_reg *reladdr;
-
- bool negate;
- bool abs;
-
- /** Register region horizontal stride */
- uint8_t stride;
-};
-
-static inline fs_reg
-retype(fs_reg reg, unsigned type)
-{
- reg.fixed_hw_reg.type = reg.type = type;
- return reg;
-}
-
-static inline fs_reg
-offset(fs_reg reg, unsigned delta)
-{
- assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
- reg.reg_offset += delta;
- return reg;
-}
-
-static inline fs_reg
-byte_offset(fs_reg reg, unsigned delta)
-{
- assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
- reg.subreg_offset += delta;
- return reg;
-}
-
-/**
- * Get either of the 8-component halves of a 16-component register.
- *
- * Note: this also works if \c reg represents a SIMD16 pair of registers.
- */
-static inline fs_reg
-half(const fs_reg ®, unsigned idx)
-{
- assert(idx < 2);
- assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
- return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
-}
-
-static const fs_reg reg_undef;
-static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
-static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
-static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
-
-class ip_record : public exec_node {
-public:
- DECLARE_RALLOC_CXX_OPERATORS(ip_record)
-
- ip_record(int ip)
- {
- this->ip = ip;
- }
-
- int ip;
-};
-
-class fs_visitor;
-
-class fs_inst : public backend_instruction {
-public:
- DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
-
- void init();
-
- fs_inst();
- fs_inst(enum opcode opcode);
- fs_inst(enum opcode opcode, fs_reg dst);
- fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
- fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
- fs_inst(enum opcode opcode, fs_reg dst,
- fs_reg src0, fs_reg src1,fs_reg src2);
-
- bool equals(fs_inst *inst) const;
- bool overwrites_reg(const fs_reg ®) const;
- bool is_send_from_grf() const;
- bool is_partial_write() const;
- int regs_read(fs_visitor *v, int arg) const;
-
- bool reads_flag() const;
- bool writes_flag() const;
-
- fs_reg dst;
- fs_reg src[3];
-
- uint32_t texture_offset; /**< Texture offset bitfield */
- uint32_t offset; /* spill/unspill offset */
-
- uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
-
- /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
- * mod and predication.
- */
- uint8_t flag_subreg;
-
- uint8_t mlen; /**< SEND message length */
- uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
- int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
- uint8_t sampler;
- uint8_t target; /**< MRT target. */
- bool saturate:1;
- bool eot:1;
- bool header_present:1;
- bool shadow_compare:1;
- bool force_uncompressed:1;
- bool force_sechalf:1;
- bool force_writemask_all:1;
-};
-
/**
* The fragment shader front-end.
*
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.h b/src/mesa/drivers/dri/i965/brw_fs_emit.h
new file mode 100644
index 0000000..1b1e584
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <eric at anholt.net>
+ *
+ */
+
+#ifndef BRW_FS_EMIT_H
+#define BRW_FS_EMIT_H
+
+extern "C" {
+#include <sys/types.h>
+#include "brw_shader.h"
+}
+
+#include "glsl/glsl_types.h"
+#include "glsl/ralloc.h"
+#include "brw_reg.h"
+
+class fs_reg {
+public:
+ DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
+
+ void init();
+
+ fs_reg();
+ fs_reg(float f);
+ fs_reg(int32_t i);
+ fs_reg(uint32_t u);
+ fs_reg(struct brw_reg fixed_hw_reg);
+ fs_reg(enum register_file file, int reg);
+ fs_reg(enum register_file file, int reg, uint32_t type);
+ fs_reg(backend_emitter *e, const struct glsl_type *type);
+
+ bool equals(const fs_reg &r) const;
+ bool is_zero() const;
+ bool is_one() const;
+ bool is_null() const;
+ bool is_valid_3src() const;
+ bool is_contiguous() const;
+ bool is_accumulator() const;
+
+ fs_reg &apply_stride(unsigned stride);
+ /** Smear a channel of the reg to all channels. */
+ fs_reg &set_smear(unsigned subreg);
+
+ /** Register file: GRF, MRF, IMM. */
+ enum register_file file;
+ /** Register type. BRW_REGISTER_TYPE_* */
+ uint8_t type;
+ /**
+ * Register number. For MRF, it's the hardware register. For
+ * GRF, it's a virtual register number until register allocation
+ */
+ uint16_t reg;
+ /**
+ * Offset from the start of the contiguous register block.
+ *
+ * For pre-register-allocation GRFs, this is in units of a float per pixel
+ * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
+ * For uniforms, this is in units of 1 float.
+ */
+ int reg_offset;
+ /**
+ * Offset in bytes from the start of the register. Values up to a
+ * backend_reg::reg_offset unit are valid.
+ */
+ int subreg_offset;
+
+ /** Value for file == IMM */
+ union {
+ int32_t i;
+ uint32_t u;
+ float f;
+ } imm;
+
+ struct brw_reg fixed_hw_reg;
+
+ fs_reg *reladdr;
+
+ bool negate;
+ bool abs;
+
+ /** Register region horizontal stride */
+ uint8_t stride;
+};
+
+static inline fs_reg
+retype(fs_reg reg, unsigned type)
+{
+ reg.fixed_hw_reg.type = reg.type = type;
+ return reg;
+}
+
+static inline fs_reg
+offset(fs_reg reg, unsigned delta)
+{
+ assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
+ reg.reg_offset += delta;
+ return reg;
+}
+
+static inline fs_reg
+byte_offset(fs_reg reg, unsigned delta)
+{
+ assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
+ reg.subreg_offset += delta;
+ return reg;
+}
+
+/**
+ * Get either of the 8-component halves of a 16-component register.
+ *
+ * Note: this also works if \c reg represents a SIMD16 pair of registers.
+ */
+static inline fs_reg
+half(const fs_reg ®, unsigned idx)
+{
+ assert(idx < 2);
+ assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
+ return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
+}
+
+static const fs_reg reg_undef;
+static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
+static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
+
+class ip_record : public exec_node {
+public:
+ DECLARE_RALLOC_CXX_OPERATORS(ip_record)
+
+ ip_record(int ip)
+ {
+ this->ip = ip;
+ }
+
+ int ip;
+};
+
+class fs_visitor;
+
+class fs_inst : public backend_instruction {
+public:
+ DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
+
+ void init();
+
+ fs_inst();
+ fs_inst(enum opcode opcode);
+ fs_inst(enum opcode opcode, fs_reg dst);
+ fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
+ fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
+ fs_inst(enum opcode opcode, fs_reg dst,
+ fs_reg src0, fs_reg src1,fs_reg src2);
+
+ bool equals(fs_inst *inst) const;
+ bool overwrites_reg(const fs_reg ®) const;
+ bool is_send_from_grf() const;
+ bool is_partial_write() const;
+ int regs_read(fs_visitor *v, int arg) const;
+
+ bool reads_flag() const;
+ bool writes_flag() const;
+
+ fs_reg dst;
+ fs_reg src[3];
+
+ /** @{
+ * Annotation for the generated IR. One of the two can be set.
+ */
+ const void *ir;
+ const char *annotation;
+ /** @} */
+
+ uint32_t texture_offset; /**< Texture offset bitfield */
+ uint32_t offset; /* spill/unspill offset */
+
+ uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
+
+ /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
+ * mod and predication.
+ */
+ uint8_t flag_subreg;
+
+ uint8_t mlen; /**< SEND message length */
+ uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
+ int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
+ uint8_t sampler;
+ uint8_t target; /**< MRT target. */
+ bool saturate:1;
+ bool eot:1;
+ bool header_present:1;
+ bool shadow_compare:1;
+ bool force_uncompressed:1;
+ bool force_sechalf:1;
+ bool force_writemask_all:1;
+};
+
+#endif /* BRW_FS_EMIT_H */
--
1.8.3.1
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