[Mesa-dev] [RFC PATCH 07/16] i965/gen6 depth surface: calculate LOD being rendered to

[Jordan Justen]

(08ef1dd for gen6)

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/gen6_blorp.cpp     | 3 +++
 src/mesa/drivers/dri/i965/gen6_depth_state.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index d434134..3f6b929 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -795,6 +795,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
    uint32_t surftype;
    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
    GLenum gl_target = params->depth.mt->target;
+   unsigned int lod;
 
    switch (gl_target) {
    case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -818,6 +819,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
                                    NULL,
                                    &tile_mask_x, &tile_mask_y);
 
+   lod = params->depth.level - params->depth.mt->first_level;
+
    /* 3DSTATE_DEPTH_BUFFER */
    {
       uint32_t tile_x = draw_x & tile_mask_x;
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index d10eb14..0fd8882 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -137,6 +137,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
    uint32_t surftype;
    unsigned int depth = 1;
    GLenum gl_target = GL_TEXTURE_2D;
+   unsigned int lod;
    const struct intel_renderbuffer *irb = NULL;
    const struct gl_renderbuffer *rb = NULL;
 
@@ -187,6 +188,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
       break;
    }
 
+   lod = irb ? irb->mt_level - irb->mt->first_level : 0;
+
    unsigned int len;
    if (brw->gen >= 6)
       len = 7;
-- 
2.0.0.rc4