[Mesa-dev] [RFC PATCH 03/16] i965/gen6: Align height to 2 with MSAA for certain surface heights

[Jordan Justen]

TODO: Find a good documented reason for this change.

This could be related to PRM Volume 1 Part 1: Graphics Core, Section
7.18.3.7.1 (Surface Arrays For all surfaces other than separate
stencil buffer):

 "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the
  value calculated in the equation above , for every other odd Surface
  Height starting from 1 i.e. 1,5,9,13"

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/gen6_surface_state.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index 728488a..715111f 100644
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -101,8 +101,12 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
    /* reloc */
    surf[1] = mt->bo->offset64;
 
+   int height0 = irb->mt->logical_height0;
+   if (brw->gen == 6 && irb->mt->num_samples > 1 && (height0 % 4) == 1)
+      height0 = ALIGN(height0, 2);
+
    surf[2] = ((irb->mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
-	      (irb->mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT |
+	      (height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT |
               ((irb->mt_level - irb->mt->first_level)) << BRW_SURFACE_LOD_SHIFT);
 
    surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
-- 
2.0.0.rc4